From: Aaron Nyholm <aaron.nyh...@southerninnovation.com>
---
bsps/include/dev/spi/xqspipsu_hw.h | 15 ++++++++-------
bsps/shared/dev/spi/xqspipsu_control.c | 7 ++++---
bsps/shared/dev/spi/xqspipsu_hw.c | 5 +++--
bsps/shared/dev/spi/xqspipsu_options.c | 9 +++++----
4 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/bsps/include/dev/spi/xqspipsu_hw.h
b/bsps/include/dev/spi/xqspipsu_hw.h
index a798f9bb89..61e7b3a240 100644
--- a/bsps/include/dev/spi/xqspipsu_hw.h
+++ b/bsps/include/dev/spi/xqspipsu_hw.h
@@ -43,6 +43,7 @@ extern "C" {
/***************************** Include Files *********************************/
+#include <bsp.h>
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
@@ -57,13 +58,13 @@ extern "C" {
/**
* QSPI Base Address
*/
-#if defined (versal)
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
#define XQSPIPS_BASEADDR 0XF1030000U
#else
#define XQSPIPS_BASEADDR 0XFF0F0000U
#endif
-#if defined (versal)
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
#define XQSPIPSU_BASEADDR 0XF1030100U
#else
#define XQSPIPSU_BASEADDR 0xFF0F0100U
@@ -141,7 +142,7 @@ extern "C" {
/**
* Register: XQSPIPSU_LQSPI
*/
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U /**< LQSPI mode enable */
#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U /**< Both memories or
one */
@@ -503,7 +504,7 @@ extern "C" {
#define XQSPIPSU_SEL_SHIFT 0U
#define XQSPIPSU_SEL_WIDTH 1U
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
#define XQSPIPSU_SEL_LQSPI_MASK 0X0U
#endif
#define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U
@@ -938,19 +939,19 @@ extern "C" {
* Tapdelay Bypass register
*/
-#if defined versal
+#if defined LIBBSP_AARCH64_XILINX_VERSAL_BSP_H
#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU
#else
#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U
#endif
#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U
#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
#endif
-#if defined versal
+#if defined LIBBSP_AARCH64_XILINX_VERSAL_BSP_H
#define IOU_TAPDLY_RESET_STATE 0x4U
#else
#define IOU_TAPDLY_RESET_STATE 0x7U
diff --git a/bsps/shared/dev/spi/xqspipsu_control.c
b/bsps/shared/dev/spi/xqspipsu_control.c
index af2400bf4c..f51e335b60 100644
--- a/bsps/shared/dev/spi/xqspipsu_control.c
+++ b/bsps/shared/dev/spi/xqspipsu_control.c
@@ -30,6 +30,7 @@
/***************************** Include Files *********************************/
+#include <bsp.h>
#include "xqspipsu_control.h"
/************************** Constant Definitions *****************************/
@@ -241,7 +242,7 @@ s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu
*InstancePtr, u8 Prescaler)
FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
-#if defined (versal)
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
if (FreqDiv <= XQSPIPSU_FREQ_37_5MHZ) {
#else
if (FreqDiv <= XQSPIPSU_FREQ_40MHZ) {
@@ -252,7 +253,7 @@ s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu
*InstancePtr, u8 Prescaler)
Tapdelay |= (TAPDLY_BYPASS_VALVE_100MHZ <<
IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
LBkModeReg |= (USE_DLY_LPBK <<
XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);
-#if defined (versal)
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
delayReg |= (u32)USE_DATA_DLY_ADJ <<
XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT;
#else
@@ -261,7 +262,7 @@ s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu
*InstancePtr, u8 Prescaler)
((u32)DATA_DLY_ADJ_DLY
<< XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);
#endif
} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {
-#if defined (versal)
+#if defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
LBkModeReg |= (USE_DLY_LPBK <<
XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT) |
(LPBK_DLY_ADJ_DLY1 <<
XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT);
#else
diff --git a/bsps/shared/dev/spi/xqspipsu_hw.c
b/bsps/shared/dev/spi/xqspipsu_hw.c
index 6f7708893f..379786ff03 100644
--- a/bsps/shared/dev/spi/xqspipsu_hw.c
+++ b/bsps/shared/dev/spi/xqspipsu_hw.c
@@ -34,6 +34,7 @@
/***************************** Include Files *********************************/
+#include <bsp.h>
#include "xqspipsu.h"
#include "xqspipsu_control.h"
#if defined (__aarch64__)
@@ -744,11 +745,11 @@ s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr,
u32 TapdelayBypass,
if (InstancePtr->IsBusy == (u32)TRUE) {
Status = (s32)XST_DEVICE_BUSY;
} else {
-#if defined (__aarch64__) && (EL1_NONSECURE == 1) && !defined (versal)
+#if defined (__aarch64__) && (EL1_NONSECURE == 1) && !defined
(LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
IOU_TAPDLY_BYPASS_OFFSET) | ((u64)(0x4) << 32),
(u64)TapdelayBypass, 0, 0, 0, 0, 0);
-#elif defined (versal)
+#elif defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
XQspiPsu_WriteReg(XQSPIPS_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
TapdelayBypass);
#else
diff --git a/bsps/shared/dev/spi/xqspipsu_options.c
b/bsps/shared/dev/spi/xqspipsu_options.c
index c889d64abb..d1a286173d 100644
--- a/bsps/shared/dev/spi/xqspipsu_options.c
+++ b/bsps/shared/dev/spi/xqspipsu_options.c
@@ -54,6 +54,7 @@
/***************************** Include Files *********************************/
+#include <bsp.h>
#include "xqspipsu_control.h"
/************************** Constant Definitions *****************************/
@@ -80,7 +81,7 @@ static OptionsMap OptionsTable[] = {
{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
{XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_CFG_WP_HOLD_MASK},
#endif
};
@@ -117,7 +118,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
{
u32 ConfigReg;
u32 Index;
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
u32 QspiPsuOptions;
#endif
s32 Status;
@@ -136,7 +137,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
} else {
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPSU_CFG_OFFSET);
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
QspiPsuOptions = OptionsVal & XQSPIPSU_LQSPI_MODE_OPTION;
OptionsVal &= (~XQSPIPSU_LQSPI_MODE_OPTION);
#endif
@@ -164,7 +165,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
if ((OptionsVal & XQSPIPSU_MANUAL_START_OPTION) != (u32)FALSE) {
InstancePtr->IsManualstart = (u8)TRUE;
}
-#if !defined (versal)
+#if !defined (LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
if ((QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) !=
(u32)FALSE) {
if ((Options & XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB) !=
(u32)FALSE) {
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);
--
2.25.1
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