On 03.08.23 15:29, Kevin Eyssartier wrote:
This commit add support for the CV32A6 processor in the rv32imac configuration.
The CORE-V CVA6 is an application class 6 stage RISC-V CPU capable of booting
Linux.
It support multiple configurations : ISA (IMACFDB), XLEN 32 and 64,
configurable cache size, TLBs, PTW and branch prediction.
It is maintained by the not-for-profit [OpenHW
Group](https://www.openhwgroup.org/).
Its code is under the Solderpad Hardware License which is based closely on the
Apache Licese Version 2.0.
It can be found at
[https://github.com/openhardware/cva6](https://github.com/openhardware/cva6).
This commit support the cv32a6_imac_sv[0|32] configurations.
RTEMS has been tested on the [Genesys2 Digilent FPGA
Board](https://digilent.com/reference/programmable-logic/genesys-2/start).
---
bsps/riscv/riscv/config/cv32a6.cfg | 9 +++++++++
The *.cfg files are no longer used.
spec/build/bsps/riscv/riscv/bspcv32a6.yml | 19 +++++++++++++++++++
spec/build/cpukit/optarchbits.yml | 1 +
3 files changed, 29 insertions(+)
create mode 100644 bsps/riscv/riscv/config/cv32a6.cfg
create mode 100644 spec/build/bsps/riscv/riscv/bspcv32a6.yml
Why do you need this BSP variant? Can't you use the rv32imac BSP?
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