On 16/03/2020 14:59, Hesham Almatary wrote:
On Mon, 16 Mar 2020 at 13:35, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
On 16/03/2020 14:33, Hesham Almatary wrote:
Sebastian, I modified my patch set to properly add the XLEN option.
This should make it generic enough for other architectures to be built
with Clang/LLVM, but I have only tested RISC-V.
I can git send-email if you want me to.
[1]https://github.com/CTSRD-CHERI/rtems/compare/967b62464bf39602f8b0f2baf57617ad74c3643d...cbe9d2a40fade836667fe2a910b9c2f85866699c
I think we need a better name for the XLEN. It is a bit RISCV-specific.
What about ARCH_BITS?
Makes more sense. I modified it accordingly
https://github.com/CTSRD-CHERI/rtems/compare/967b62464bf39602f8b0f2baf57617ad74c3643d...8847fa44e68a0d7e0f9e96faf54c88928f8ac141
Ok, could you please send the patches which you want to get integrated
in build branch to the mailing list.
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