----- Am 13. Jan 2019 um 0:09 schrieb Jiri Gaisler j...@gaisler.se: > On 1/11/19 1:36 PM, Jiri Gaisler wrote: >> On 1/9/19 10:46 AM, Sebastian Huber wrote: >>> Hello Jiri, >>> >>> could you please rebase your work to this RTEMS commit: >>> >>> https://git.rtems.org/rtems/commit/?id=b9ffc41c9678fb3c5386c1a6ab394656ec85dbc6 >>> >> This works fine for me - I can now pass all uni-processor tests. On SMP, I >> still >> have a few fails but I think they are related to the simulator and the >> compressed RISC-V instruction set. I will investigate further ... > > The atomic LR/SC instructions did not work as expected in the simulator, which > caused the failures. After cleaning that up, all tests now pass. I have tested > up to 4 cpus and various frequencies and time slots in the sim with no fails, > so it seems fairly robust. I will clean up my bsp sources and post the patches > on the list for review. I will also provide a patch for the RISC-V version of > gdb-8.2 to add the new sim. Thanks for the help to get this going..! > > > $ rtems-test --rtems-bsp=riscv-sis riscv-rtems5/c/grlib/testsuites > --log=all.txt > > > Passed: 630 > Failed: 0 > User Input: 5 > Expected Fail: 0 > Indeterminate: 0 > Benchmark: 3 > Timeout: 0 > Invalid: 0 > Wrong Version: 0 > Wrong Build: 0 > Wrong Tools: 0 > ------------------ > Total: 638 > User Input: > monitor.exe > termios.exe > top.exe > capture.exe > fileio.exe > Benchmark: > linpack.exe > dhrystone.exe > whetstone.exe > Average test time: 0:00:00.732410 > Testing time : 0:07:47.277261
This is really great. This is the second free simulator (the other is SIS) which is capable enough to run all tests successfully. We should think about making a RISC-V BSP the default in the documentation instead of erc32. _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
