https://docs.rtems.org/branches/master/cpu-supplement/port.html#interrupt-processing
https://docs.rtems.org/branches/master/bsp-howto.html#set-vector-install-an-interrupt-vector On Fri, Jun 30, 2017 at 10:49 AM, Denis Obrezkov <denisobrez...@gmail.com> wrote: > Hello all, > what is the common practice of interrupt implementation in RTEMS? > I wasn't able to find much information in RTEMS BSP manual. > > My platform RISC-V has vectored interrupts and exceptions. > A cause of an exception or of an interrupt is always available in 'mcause' > register. > But for interrupts an address of a handlers' table can also be dynamically > provided. > So, what should I do in order to implement interrupt handlers? > What is the consequence of steps when interrupt appears (save stack, make a > routine...)? > Also, what is a good example of a BSP which implements ISR in a proper way? > > -- > Regards, Denis Obrezkov > > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
