Update #2751.
---
cpukit/score/include/rtems/score/percpu.h | 14 +++++++++++++-
cpukit/score/src/percpuasm.c | 6 ++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/cpukit/score/include/rtems/score/percpu.h
b/cpukit/score/include/rtems/score/percpu.h
index ae789b8..d2025c0 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -290,6 +290,16 @@ typedef struct Per_CPU_Control {
uint32_t isr_nest_level;
/**
+ * @brief Indicetes if an ISR thread dispatch is disabled.
+ *
+ * This flag is context switched with each thread. It indicates that this
+ * thread has an interrupt stack frame on its stack. By using this flag, we
+ * can avoid nesting more interrupt dispatching attempts on a previously
+ * interrupted thread's stack.
+ */
+ uint32_t isr_dispatch_disable;
+
+ /**
* @brief The thread dispatch critical section nesting counter which is used
* to prevent context switches at inopportune moments.
*/
@@ -780,8 +790,10 @@ RTEMS_INLINE_ROUTINE struct _Thread_Control
*_Thread_Get_executing( void )
*/
#define PER_CPU_ISR_NEST_LEVEL \
PER_CPU_END_STACK
-#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \
+#define PER_CPU_ISR_DISPATCH_DISABLE \
PER_CPU_ISR_NEST_LEVEL + 4
+#define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \
+ PER_CPU_ISR_DISPATCH_DISABLE + 4
#define PER_CPU_OFFSET_EXECUTING \
PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL + 4
#define PER_CPU_OFFSET_HEIR \
diff --git a/cpukit/score/src/percpuasm.c b/cpukit/score/src/percpuasm.c
index 53e6326..29bdb13 100644
--- a/cpukit/score/src/percpuasm.c
+++ b/cpukit/score/src/percpuasm.c
@@ -84,6 +84,12 @@ RTEMS_STATIC_ASSERT(
);
RTEMS_STATIC_ASSERT(
+ offsetof(Per_CPU_Control, isr_dispatch_disable)
+ == PER_CPU_ISR_DISPATCH_DISABLE,
+ PER_CPU_ISR_DISPATCH_DISABLE
+);
+
+RTEMS_STATIC_ASSERT(
offsetof(Per_CPU_Control, thread_dispatch_disable_level)
== PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL,
PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL
--
1.8.4.5
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