Update #2751.
---
c/src/lib/libbsp/sparc/shared/irq_asm.S | 10 +++++-----
cpukit/score/cpu/sparc/cpu.c | 6 ------
cpukit/score/cpu/sparc/rtems/score/cpuimpl.h | 21 +++++----------------
3 files changed, 10 insertions(+), 27 deletions(-)
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S
b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index a842a62..fc89932 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -74,7 +74,7 @@ SYM(_CPU_Context_switch):
std %o6, [%o0 + O6_SP_OFFSET] ! save the output registers
! load the ISR stack nesting prevention flag
- ld [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %o4
+ ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
! save it a bit later so we do not waste a couple of cycles
rd %psr, %o2
@@ -217,7 +217,7 @@ done_flushing:
ldd [%o1 + L6_OFFSET], %l6
! Now restore thread specific ISR dispatch prevention flag
- st %o2, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
+ st %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
ldd [%o1 + I0_OFFSET], %i0 ! restore the input registers
ldd [%o1 + I2_OFFSET], %i2
@@ -594,7 +594,7 @@ profiling_not_outer_most_exit:
nop
! Are we dispatching from a previous ISR in the interrupted thread?
- ld [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %l7
+ ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %l7
orcc %l7, %g0, %g0 ! Is this thread already doing an ISR?
bnz simple_return ! Yes, then do a "simple" exit
nop
@@ -617,7 +617,7 @@ profiling_not_outer_most_exit:
! Set ISR dispatch nesting prevention flag
mov 1,%l6
- st %l6, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
+ st %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
/*
* The following subtract should get us back on the interrupted
@@ -726,7 +726,7 @@ thread_dispatch_done:
! No, then clear out and return
! Zero out ISR stack nesting prevention flag
- st %g0, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
+ st %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
/*
* The CWP in place at this point may be different from
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 4aa30db..a640849 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -23,12 +23,6 @@
#include <rtems/score/tls.h>
#include <rtems/rtems/cache.h>
-RTEMS_STATIC_ASSERT(
- offsetof( Per_CPU_Control, cpu_per_cpu.isr_dispatch_disable)
- == SPARC_PER_CPU_ISR_DISPATCH_DISABLE,
- SPARC_PER_CPU_ISR_DISPATCH_DISABLE
-);
-
#if SPARC_HAS_FPU == 1
RTEMS_STATIC_ASSERT(
offsetof( Per_CPU_Control, cpu_per_cpu.fsr)
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
index 51071ab..5563db8 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
@@ -70,21 +70,15 @@
#if ( SPARC_HAS_FPU == 1 )
#define CPU_PER_CPU_CONTROL_SIZE 8
#else
- #define CPU_PER_CPU_CONTROL_SIZE 4
+ #define CPU_PER_CPU_CONTROL_SIZE 0
#endif
-/**
- * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
- * relative to the Per_CPU_Control begin.
- */
-#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
-
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
* Per_CPU_Control begin.
*/
- #define SPARC_PER_CPU_FSR_OFFSET 4
+ #define SPARC_PER_CPU_FSR_OFFSET 0
#endif
#ifndef ASM
@@ -94,14 +88,6 @@ extern "C" {
#endif
typedef struct {
- /**
- * This flag is context switched with each thread. It indicates
- * that THIS thread has an _ISR_Dispatch stack frame on its stack.
- * By using this flag, we can avoid nesting more interrupt dispatching
- * attempts on a previously interrupted thread's stack.
- */
- uint32_t isr_dispatch_disable;
-
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Memory location to store the FSR register during interrupt
@@ -111,6 +97,9 @@ typedef struct {
* floating point operations in progress.
*/
uint32_t fsr;
+
+ /* See Per_CPU_Control::Interrupt_frame */
+ uint32_t reserved_for_alignment_of_interrupt_frame;
#endif
} CPU_Per_CPU_control;
--
1.8.4.5
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