--- c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c | 15 +++++++++++++++ c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c | 7 +++++++ 2 files changed, 22 insertions(+)
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c index 3940352..310014d 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c @@ -14,9 +14,24 @@ #include <rtems/score/smpimpl.h> +extern void _start(void); + bool _CPU_SMP_Start_processor(uint32_t cpu_index) { /* + * Enable the second CPU. + */ + if (cpu_index != 0) { + volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL; + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); + *kick_address = (uint32_t) _start; + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); + _ARM_Send_event(); + } + + /* * Wait for secondary processor to complete its basic initialization so that * we can enable the unified L2 cache. */ diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c index c7a1089..e0a7743 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstartmmu.c @@ -22,6 +22,13 @@ BSP_START_DATA_SECTION static const arm_cp15_start_section_config zynq_mmu_config_table[] = { ARMV7_CP15_START_DEFAULT_SECTIONS, +#if defined(RTEMS_SMP) + { + .begin = 0xffff0000U, + .end = 0xffffffffU, + .flags = ARMV7_MMU_DEVICE + }, +#endif { .begin = 0xe0000000U, .end = 0xe0200000U, -- 2.3.0 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel