On Fri, Oct 24, 2014 at 1:36 AM, Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > On 23/10/14 19:41, Gedare Bloom wrote: >> >> We might consider removing the cache manager in favor of making dcache >> flush/invalidate and icache invalidate lines part of the score/cpu >> port (are they the same across cpu's in the same arch family?) > > > No, the caches are highly chip specific. > OK. I just grepped and I don't see any CPU_cache being used from anywhere except bsp code. I suspect we should give this framework the axe, or reduce it drastically and move it into the BSP layer.
> > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
