On 23/10/14 19:41, Gedare Bloom wrote:
We might consider removing the cache manager in favor of making dcache flush/invalidate and icache invalidate lines part of the score/cpu port (are they the same across cpu's in the same arch family?)
No, the caches are highly chip specific. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
