Add the pcie-upstream-port and pcie-downstream-port devices to the latest x86_64 capabilities data and update the x-width and x-speed properties to be non-experimental.
See QEMU commits 432b3f707a3c (hw/pci-bridge: Make speed and width for PCIe ports non-experimental) and 73962cc5f06a (hw/pci-bridge: Add generic PCIe switch upstream and downstream ports). Signed-off-by: David Vrabel <[email protected]> --- This should be replace with a more comprehensive refresh the the capability data from QEMU. --- .../qemucapabilitiesdata/caps_11.2.0_x86_64.replies | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/tests/qemucapabilitiesdata/caps_11.2.0_x86_64.replies b/tests/qemucapabilitiesdata/caps_11.2.0_x86_64.replies index c4612260f3..d453637926 100644 --- a/tests/qemucapabilitiesdata/caps_11.2.0_x86_64.replies +++ b/tests/qemucapabilitiesdata/caps_11.2.0_x86_64.replies @@ -28463,6 +28463,14 @@ { "name": "SapphireRapids-v7-x86_64-cpu", "parent": "x86_64-cpu" + }, + { + "name": "pcie-upstream-port", + "parent": "pcie-port" + }, + { + "name": "pcie-downstream-port", + "parent": "pcie-slot" } ], "id": "libvirt-6" @@ -32715,7 +32723,7 @@ }, { "default-value": "32", - "name": "x-width", + "name": "width", "description": "1/2/4/8/12/16/32", "type": "PCIELinkWidth" }, @@ -32731,7 +32739,7 @@ }, { "default-value": "16", - "name": "x-speed", + "name": "speed", "description": "2_5/5/8/16/32/64", "type": "PCIELinkSpeed" }, -- 2.43.0
