Source: openlibm Version: 0.7.0+dfsg-2 Severity: normal Tags: ftbfs, patch User: debian-ri...@lists.debian.org Usertags: riscv64 X-Debbugs-Cc: debian-ri...@lists.debian.org
Dear openlibm Maintainer, The openlibm has a ftbfs issue on riscv64 arch: ``` No rule to make target 'riscv64/Make.files' ``` The buildd log is here: https://buildd.debian.org/status/fetch.php?pkg=openlibm&arch=riscv64&ver=0.7.0%2Bdfsg-2&stamp=1593571040&raw=0 There are two solutions to this issues: One: Upgrade openlibm to 0.81[0]. The PR has enable openlibm to support riscv64; Two: The patches attached are to fix the issue and I can build the package on my real riscv64 hardware(Unmatched board) with it if it is not convenient to upgrade here for openlibm. Please let me know if here need me to do more tests. Bo [0]: https://github.com/JuliaMath/openlibm/commit/428e7af2148894e287801a0539b7a1756f451e88 -- Best Regards,
# SymbolsHelper-Confirmed: 0.7.0 amd64 arm64 armel armhf i386 mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x sh4 sparc64 libopenlibm.so.3 libopenlibm3 #MINVER# * Build-Depends-Package: libopenlibm-dev (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_aT@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_atanhi@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_atanlo@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS0@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS1@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS2@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS3@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS4@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS5@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pS6@Base 0.4 (arch=arm64)_ItL_pS7@Base 0.6.0 (arch=arm64)_ItL_pS8@Base 0.6.0 (arch=arm64)_ItL_pS9@Base 0.6.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_pi_lo@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_qS1@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_qS2@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_qS3@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_qS4@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)_ItL_qS5@Base 0.4 (arch=arm64)_ItL_qS6@Base 0.6.0 (arch=arm64)_ItL_qS7@Base 0.6.0 (arch=arm64)_ItL_qS8@Base 0.6.0 (arch=arm64)_ItL_qS9@Base 0.6.0 __exp__D@Base 0.4 __fe_dfl_env@Base 0.4 #MISSING: 0.5.0# (arch=!armhf)__fedisableexcept@Base 0.4 #MISSING: 0.5.0# (arch=!armhf)__feenableexcept@Base 0.4 __fpclassifyd@Base 0.4 __fpclassifyf@Base 0.4 (arch=!armhf)__fpclassifyl@Base 0.4 (arch=i386 kfreebsd-i386 hurd-i386)__has_sse@Base 0.4 __ieee754_rem_pio2@Base 0.4 __ieee754_rem_pio2f@Base 0.4 __isfinite@Base 0.4 __isfinitef@Base 0.4 (arch=!armhf)__isfinitel@Base 0.4 __isinff@Base 0.4 (arch=!armhf)__isinfl@Base 0.4 __isnanf@Base 0.4 (arch=!armhf)__isnanl@Base 0.4 __isnormal@Base 0.4 __isnormalf@Base 0.4 (arch=!armhf)__isnormall@Base 0.4 __kernel_cos@Base 0.4 __kernel_cosdf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)__kernel_cosl@Base 0.4 __kernel_rem_pio2@Base 0.4 __kernel_sin@Base 0.4 #MISSING: 0.5.0# __kernel_sincos@Base 0.4 #MISSING: 0.5.0# __kernel_sincosdf@Base 0.4 __kernel_sindf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)__kernel_sinl@Base 0.4 __kernel_tan@Base 0.4 __kernel_tandf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)__kernel_tanl@Base 0.4 __ldexp_cexp@Base 0.4 __ldexp_cexpf@Base 0.4 __ldexp_exp@Base 0.4 __ldexp_expf@Base 0.4 __log__D@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)__p1evll@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)__polevll@Base 0.5.0 __scan_nan@Base 0.5.0 __signbit@Base 0.4 __signbitf@Base 0.4 (arch=!armhf)__signbitl@Base 0.4 (arch=i386 kfreebsd-i386 hurd-i386)__test_sse@Base 0.4 #MISSING: 0.5.0# _scan_nan@Base 0.4 acos@Base 0.4 acosf@Base 0.4 acosh@Base 0.4 acoshf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)acoshl@Base 0.5.0 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)acosl@Base 0.4 asin@Base 0.4 asinf@Base 0.4 asinh@Base 0.4 asinhf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)asinhl@Base 0.5.0 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)asinl@Base 0.4 atan2@Base 0.4 atan2f@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)atan2l@Base 0.4 atan@Base 0.4 atanf@Base 0.4 atanh@Base 0.4 atanhf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)atanhl@Base 0.5.0 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)atanl@Base 0.4 cabs@Base 0.4 cabsf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)cabsl@Base 0.4 cacos@Base 0.5.0 cacosf@Base 0.5.0 cacosh@Base 0.5.0 cacoshf@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cacoshl@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cacosl@Base 0.5.0 carg@Base 0.4 cargf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cargl@Base 0.4 casin@Base 0.5.0 casinf@Base 0.5.0 casinh@Base 0.5.0 casinhf@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)casinhl@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)casinl@Base 0.5.0 catan@Base 0.5.0 catanf@Base 0.5.0 catanh@Base 0.5.0 catanhf@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)catanhl@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)catanl@Base 0.5.0 cbrt@Base 0.4 cbrtf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cbrtl@Base 0.5.0 ccos@Base 0.4 ccosf@Base 0.4 ccosh@Base 0.4 ccoshf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)ccoshl@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)ccosl@Base 0.5.0 ceil@Base 0.4 ceilf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)ceill@Base 0.4 cexp@Base 0.4 cexpf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cexpl@Base 0.5.0 cimag@Base 0.4 cimagf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cimagl@Base 0.4 clog@Base 0.5.0 clogf@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)clogl@Base 0.5.0 conj@Base 0.4 conjf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)conjl@Base 0.4 copysign@Base 0.4 copysignf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)copysignl@Base 0.4 cos@Base 0.4 cosf@Base 0.4 cosh@Base 0.4 coshf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)coshl@Base 0.5.0 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)cosl@Base 0.4 cpow@Base 0.4 cpowf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cpowl@Base 0.4 cproj@Base 0.4 cprojf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)cprojl@Base 0.4 creal@Base 0.4 crealf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)creall@Base 0.4 csin@Base 0.4 csinf@Base 0.4 csinh@Base 0.4 csinhf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)csinhl@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)csinl@Base 0.5.0 csqrt@Base 0.4 csqrtf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)csqrtl@Base 0.4 ctan@Base 0.4 ctanf@Base 0.4 ctanh@Base 0.4 ctanhf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)ctanhl@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)ctanl@Base 0.5.0 #MISSING: 0.5.0# drem@Base 0.4 #MISSING: 0.5.0# dremf@Base 0.4 erf@Base 0.4 erfc@Base 0.4 erfcf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)erfcl@Base 0.5.0 erff@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)erfl@Base 0.5.0 exp2@Base 0.4 exp2f@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)exp2l@Base 0.4 exp@Base 0.4 expf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)expl@Base 0.5.0 expm1@Base 0.4 expm1f@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)expm1l@Base 0.5.0 fabs@Base 0.4 fabsf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)fabsl@Base 0.4 fdim@Base 0.4 fdimf@Base 0.4 (arch=!armhf)fdiml@Base 0.4 (arch=arm64 armhf hurd-i386 i386 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x)feclearexcept@Base 0.7.0 (arch=!arm64 !armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)fedisableexcept@Base 0.4 (arch=!arm64 !armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)feenableexcept@Base 0.4 fegetenv@Base 0.4 (arch=arm64 armhf hurd-i386 i386 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x)fegetexceptflag@Base 0.7.0 (arch=arm64 armhf hurd-i386 i386 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x)fegetround@Base 0.7.0 feholdexcept@Base 0.4 feraiseexcept@Base 0.4 (arch=arm64 armhf hurd-i386 i386 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x)fesetenv@Base 0.7.0 fesetexceptflag@Base 0.4 (arch=arm64 armhf hurd-i386 i386 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x)fesetround@Base 0.7.0 (arch=arm64 armhf hurd-i386 i386 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el riscv64 s390x)fetestexcept@Base 0.7.0 feupdateenv@Base 0.4 #MISSING: 0.5.0# finite@Base 0.4 #MISSING: 0.5.0# finitef@Base 0.4 floor@Base 0.4 floorf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)floorl@Base 0.4 fma@Base 0.4 fmaf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)fmal@Base 0.4 fmax@Base 0.4 fmaxf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)fmaxl@Base 0.4 fmin@Base 0.4 fminf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)fminl@Base 0.4 fmod@Base 0.4 fmodf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)fmodl@Base 0.4 (arch=i386 kfreebsd-i386 hurd-i386)fpgetprec@Base 0.5.0 (arch=i386 kfreebsd-i386 hurd-i386)fpsetprec@Base 0.5.0 frexp@Base 0.4 frexpf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)frexpl@Base 0.4 #MISSING: 0.5.0# gamma@Base 0.4 #MISSING: 0.5.0# gamma_r@Base 0.4 #MISSING: 0.5.0# gammaf@Base 0.4 #MISSING: 0.5.0# gammaf_r@Base 0.4 hypot@Base 0.4 hypotf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)hypotl@Base 0.4 ilogb@Base 0.4 ilogbf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)ilogbl@Base 0.4 isinf@Base 0.4 isinff@Base 0.4 isnan@Base 0.4 isnanf@Base 0.4 isopenlibm@Base 0.4 j0@Base 0.4 j0f@Base 0.4 j1@Base 0.4 j1f@Base 0.4 jn@Base 0.4 jnf@Base 0.4 ldexp@Base 0.4 ldexpf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)ldexpl@Base 0.4 lgamma@Base 0.4 lgamma_r@Base 0.4 lgammaf@Base 0.4 lgammaf_r@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)lgammal@Base 0.5.0 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)lgammal_r@Base 0.5.0 llrint@Base 0.4 llrintf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)llrintl@Base 0.4 llround@Base 0.4 llroundf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)llroundl@Base 0.4 log10@Base 0.4 log10f@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)log10l@Base 0.5.0 log1p@Base 0.4 log1pf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)log1pl@Base 0.5.0 log2@Base 0.4 log2f@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)log2l@Base 0.5.0 log@Base 0.4 logb@Base 0.4 logbf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)logbl@Base 0.4 logf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)logl@Base 0.5.0 lrint@Base 0.4 lrintf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)lrintl@Base 0.4 lround@Base 0.4 lroundf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)lroundl@Base 0.4 modf@Base 0.4 modff@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)modfl@Base 0.4 nan@Base 0.4 nanf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)nanl@Base 0.4 nearbyint@Base 0.4 nearbyintf@Base 0.4 (arch=arm64)nearbyintl@Base 0.6.0 nextafter@Base 0.4 nextafterf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)nextafterl@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)nexttoward@Base 0.4 (arch=!armhf)nexttowardf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)nexttowardl@Base 0.4 pow@Base 0.4 powf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)powl@Base 0.5.0 remainder@Base 0.4 remainderf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)remainderl@Base 0.4 remquo@Base 0.4 remquof@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)remquol@Base 0.4 rint@Base 0.4 rintf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)rintl@Base 0.4 round@Base 0.4 roundf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)roundl@Base 0.4 #MISSING: 0.5.0# scalb@Base 0.4 #MISSING: 0.5.0# scalbf@Base 0.4 scalbln@Base 0.4 scalblnf@Base 0.4 (arch=!armhf)scalblnl@Base 0.4 scalbn@Base 0.4 scalbnf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)scalbnl@Base 0.4 signgam@Base 0.4 #MISSING: 0.5.0# significand@Base 0.4 #MISSING: 0.5.0# significandf@Base 0.4 sin@Base 0.4 sincos@Base 0.4 sincosf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)sincosl@Base 0.4 sinf@Base 0.4 sinh@Base 0.4 sinhf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)sinhl@Base 0.5.0 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)sinl@Base 0.4 sqrt@Base 0.4 sqrtf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)sqrtl@Base 0.4 tan@Base 0.4 tanf@Base 0.4 tanh@Base 0.4 tanhf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)tanhl@Base 0.5.0 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)tanl@Base 0.4 tgamma@Base 0.4 tgammaf@Base 0.4 (arch=!armhf !mips !mips64el !mipsel !powerpc !ppc64 !ppc64el !riscv64 !s390x)tgammal@Base 0.5.0 trunc@Base 0.4 truncf@Base 0.4 (arch=!mips64el !powerpc !ppc64 !ppc64el !riscv64 !s390x)truncl@Base 0.4 y0@Base 0.4 y0f@Base 0.4 y1@Base 0.4 y1f@Base 0.4 yn@Base 0.4 ynf@Base 0.4
The code refer to: https://github.com/JuliaMath/openlibm/pull/254 --- /dev/null +++ b/riscv64/Make.files @@ -0,0 +1 @@ +$(CUR_SRCS) = fenv.c --- /dev/null +++ b/riscv64/fenv.c @@ -0,0 +1,67 @@ +/*- + * Copyright (c) 2004 David Schultz <d...@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define __fenv_static +#include "openlibm_fenv.h" + +#ifdef __GNUC_GNU_INLINE__ +#error "This file must be compiled with C99 'inline' semantics" +#endif + +/* + * Hopefully the system ID byte is immutable, so it's valid to use + * this as a default environment. + */ +const fenv_t __fe_dfl_env = 0; + +#ifdef __mips_soft_float +#define __set_env(env, flags, mask, rnd) env = ((flags) \ + | (mask)<<_FPUSW_SHIFT \ + | (rnd) << 24) +#define __env_flags(env) ((env) & FE_ALL_EXCEPT) +#define __env_mask(env) (((env) >> _FPUSW_SHIFT) \ + & FE_ALL_EXCEPT) +#define __env_round(env) (((env) >> 24) & _ROUND_MASK) +#include "fenv-softfloat.h" +#endif + +extern inline int feclearexcept(int __excepts); +extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts); +extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts); +extern inline int feraiseexcept(int __excepts); +extern inline int fetestexcept(int __excepts); +extern inline int fegetround(void); +extern inline int fesetround(int __round); +extern inline int fegetenv(fenv_t *__envp); +extern inline int feholdexcept(fenv_t *__envp); +extern inline int fesetenv(const fenv_t *__envp); +extern inline int feupdateenv(const fenv_t *__envp); +extern inline int feenableexcept(int __mask); +extern inline int fedisableexcept(int __mask); +extern inline int fegetexcept(void); + --- /dev/null +++ b/src/riscv_fpmath.h @@ -0,0 +1,57 @@ +/*- + * Copyright (c) 2002, 2003 David Schultz <d...@freebsd.org> + * Copyright (c) 2014 The FreeBSD Foundation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/lib/libc/riscv/_fpmath.h 362788 2020-06-29 19:30:35Z mhorne $ + */ + +union IEEEl2bits { + long double e; + struct { + unsigned long manl :64; + unsigned long manh :48; + unsigned int exp :15; + unsigned int sign :1; + } bits; + struct { + unsigned long manl :64; + unsigned long manh :48; + unsigned int expsign :16; + } xbits; +}; + +#define LDBL_NBIT 0 +#define LDBL_IMPLICIT_NBIT +#define mask_nbit_l(u) ((void)0) + +#define LDBL_MANH_SIZE 48 +#define LDBL_MANL_SIZE 64 + +#define LDBL_TO_ARRAY32(u, a) do { \ + (a)[0] = (uint32_t)(u).bits.manl; \ + (a)[1] = (uint32_t)((u).bits.manl >> 32); \ + (a)[2] = (uint32_t)(u).bits.manh; \ + (a)[3] = (uint32_t)((u).bits.manh >> 32); \ +} while(0) --- a/src/fpmath.h +++ b/src/fpmath.h @@ -43,6 +43,8 @@ #include "mips_fpmath.h" #elif defined(__s390__) #include "s390_fpmath.h" +#elif defined(__riscv) +#include "riscv_fpmath.h" #endif /* Definitions provided directly by GCC and Clang. */ --- a/include/openlibm_fenv.h +++ b/include/openlibm_fenv.h @@ -14,6 +14,8 @@ #include <openlibm_fenv_mips.h> #elif defined(__s390__) #include <openlibm_fenv_s390.h> +#elif defined(__riscv) +#include <openlibm_fenv_riscv.h> #else #error "Unsupported platform" #endif --- /dev/null +++ b/include/openlibm_fenv_riscv.h @@ -0,0 +1,261 @@ +/*- + * Copyright (c) 2004-2005 David Schultz <d...@freebsd.org> + * Copyright (c) 2015-2016 Ruslan Bukin <b...@bsdpad.com> + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under DARPA/AFRL contract + * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Portions of this software were developed by the University of Cambridge + * Computer Laboratory as part of the CTSRD Project, with support from the + * UK Higher Education Innovation Fund (HEIF). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/lib/msun/riscv/fenv.h 332792 2018-04-19 20:36:15Z brooks $ + */ + +#ifndef _FENV_H_ +#define _FENV_H_ + +#include <stdint.h> +#include "cdefs-compat.h" + +#ifndef __fenv_static +#define __fenv_static static +#endif + +typedef __uint64_t fenv_t; +typedef __uint64_t fexcept_t; + +/* Exception flags */ +#define FE_INVALID 0x0010 +#define FE_DIVBYZERO 0x0008 +#define FE_OVERFLOW 0x0004 +#define FE_UNDERFLOW 0x0002 +#define FE_INEXACT 0x0001 +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ + FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) + +/* + * RISC-V Rounding modes + */ +#define _ROUND_SHIFT 5 +#define FE_TONEAREST (0x00 << _ROUND_SHIFT) +#define FE_TOWARDZERO (0x01 << _ROUND_SHIFT) +#define FE_DOWNWARD (0x02 << _ROUND_SHIFT) +#define FE_UPWARD (0x03 << _ROUND_SHIFT) +#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ + FE_UPWARD | FE_TOWARDZERO) + +__BEGIN_DECLS + +/* Default floating-point environment */ +extern const fenv_t __fe_dfl_env; +#define FE_DFL_ENV (&__fe_dfl_env) + +#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double) +#if defined(__riscv_float_abi_single) +#error single precision floating point ABI not supported +#else +#error compiler did not set soft/hard float macros +#endif +#endif + +#ifndef __riscv_float_abi_soft +#define __rfs(__fcsr) __asm __volatile("csrr %0, fcsr" : "=r" (__fcsr)) +#define __wfs(__fcsr) __asm __volatile("csrw fcsr, %0" :: "r" (__fcsr)) +#endif + +#ifdef __riscv_float_abi_soft +int feclearexcept(int __excepts); +int fegetexceptflag(fexcept_t *__flagp, int __excepts); +int fesetexceptflag(const fexcept_t *__flagp, int __excepts); +int feraiseexcept(int __excepts); +int fetestexcept(int __excepts); +int fegetround(void); +int fesetround(int __round); +int fegetenv(fenv_t *__envp); +int feholdexcept(fenv_t *__envp); +int fesetenv(const fenv_t *__envp); +int feupdateenv(const fenv_t *__envp); +#else +__fenv_static inline int +feclearexcept(int __excepts) +{ + + __asm __volatile("csrc fflags, %0" :: "r"(__excepts)); + + return (0); +} + +__fenv_static inline int +fegetexceptflag(fexcept_t *__flagp, int __excepts) +{ + fexcept_t __fcsr; + + __rfs(__fcsr); + *__flagp = __fcsr & __excepts; + + return (0); +} + +__fenv_static inline int +fesetexceptflag(const fexcept_t *__flagp, int __excepts) +{ + fexcept_t __fcsr; + + __fcsr = *__flagp; + __asm __volatile("csrc fflags, %0" :: "r"(__excepts)); + __asm __volatile("csrs fflags, %0" :: "r"(__fcsr & __excepts)); + + return (0); +} + +__fenv_static inline int +feraiseexcept(int __excepts) +{ + + __asm __volatile("csrs fflags, %0" :: "r"(__excepts)); + + return (0); +} + +__fenv_static inline int +fetestexcept(int __excepts) +{ + fexcept_t __fcsr; + + __rfs(__fcsr); + + return (__fcsr & __excepts); +} + +__fenv_static inline int +fegetround(void) +{ + fexcept_t __fcsr; + + __rfs(__fcsr); + + return (__fcsr & _ROUND_MASK); +} + +__fenv_static inline int +fesetround(int __round) +{ + fexcept_t __fcsr; + + if (__round & ~_ROUND_MASK) + return (-1); + + __rfs(__fcsr); + __fcsr &= ~_ROUND_MASK; + __fcsr |= __round; + __wfs(__fcsr); + + return (0); +} + +__fenv_static inline int +fegetenv(fenv_t *__envp) +{ + + __rfs(*__envp); + + return (0); +} + +__fenv_static inline int +feholdexcept(fenv_t *__envp) +{ + + /* No exception traps. */ + + return (-1); +} + +__fenv_static inline int +fesetenv(const fenv_t *__envp) +{ + + __wfs(*__envp); + + return (0); +} + +__fenv_static inline int +feupdateenv(const fenv_t *__envp) +{ + fexcept_t __fcsr; + + __rfs(__fcsr); + __wfs(*__envp); + feraiseexcept(__fcsr & FE_ALL_EXCEPT); + + return (0); +} +#endif /* !__riscv_float_abi_soft */ + +#if __BSD_VISIBLE + +/* We currently provide no external definitions of the functions below. */ + +#ifdef __riscv_float_abi_soft +int feenableexcept(int __mask); +int fedisableexcept(int __mask); +int fegetexcept(void); +#else +static inline int +feenableexcept(int __mask) +{ + + /* No exception traps. */ + + return (-1); +} + +static inline int +fedisableexcept(int __mask) +{ + + /* No exception traps. */ + + return (0); +} + +static inline int +fegetexcept(void) +{ + + /* No exception traps. */ + + return (0); +} +#endif /* !__riscv_float_abi_soft */ + +#endif /* __BSD_VISIBLE */ + +__END_DECLS + +#endif /* !_FENV_H_ */ --- a/Makefile +++ b/Makefile @@ -78,7 +78,7 @@ $(MAKE) -C test test-float clean: - rm -f aarch64/*.o amd64/*.o arm/*.o bsdsrc/*.o i387/*.o ld80/*.o ld128/*.o src/*.o powerpc/*.o mips/*.o s390/*.o + rm -f aarch64/*.o amd64/*.o arm/*.o bsdsrc/*.o i387/*.o ld80/*.o ld128/*.o src/*.o powerpc/*.o mips/*.o s390/*.o riscv64/*.o rm -f libopenlibm.a libopenlibm.*$(SHLIB_EXT)* $(MAKE) -C test clean --- a/Make.inc +++ b/Make.inc @@ -80,6 +80,10 @@ override ARCH := mips endif +ifeq ($(findstring riscv64,$(ARCH)),riscv64) +override ARCH := riscv64 +endif + # If CFLAGS does not contain a -O optimization flag, default to -O3 ifeq ($(findstring -O,$(CFLAGS)),) CFLAGS_add += -O3
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