On 3/23/10 12:10 AM, repository service wrote:
> + /* Check to see whether it took */
> + reg32 = pci_read_config32(dev, GEN_CNTL);
> + val = reg32 >> 15;
> + val &= 0x7;
> +
> + if ((val & 0x4) && (hpet == (val & 0x3))) {
> + printk_debug("HPET enabled at 0x%x\n", HPET_ADDR);
> + } else {
> + printk_err("HPET was not enabled correctly\n");
> + reg32 &= ~(1 << 17); /* Clear Enable */
> + pci_write_config32(dev, GEN_CNTL, reg32);
> + }
>
What kind of errr condition does that check for?
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
