llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-backend-x86 Author: TelGome <details> <summary>Changes</summary> Support [Packed Multiply High Parts](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-multiply-high-parts) --- Patch is 53.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225015.diff 10 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+20) - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+67-1) - (modified) clang/lib/Headers/riscv_packed_simd.h (+20) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+342-3) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+109) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+28) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+193) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+58) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+93) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+121) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index ee840e45a65ba..9065e9e363a56 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -404,6 +404,26 @@ def mulu_w11_u64 : RISCVBuiltin<"uint64_t(_Vector<2, unsigned int>, _Vector<2, u def mulsu_w00_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">; def mulsu_w11_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">; +// Packed Multiply High Parts (32-bit) +def pmulh_b0_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, signed char>)">; +def pmulh_b1_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, signed char>)">; +def pmulhsu_b0_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, unsigned char>)">; +def pmulhsu_b1_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, unsigned char>)">; +def mulh_h0_i32 : RISCVBuiltin<"int(int, _Vector<2, short>)">; +def mulh_h1_i32 : RISCVBuiltin<"int(int, _Vector<2, short>)">; +def mulhsu_h0_i32 : RISCVBuiltin<"int(int, _Vector<2, unsigned short>)">; +def mulhsu_h1_i32 : RISCVBuiltin<"int(int, _Vector<2, unsigned short>)">; + +// Packed Multiply High Parts (64-bit) +def pmulh_b0_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, signed char>)">; +def pmulh_b1_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, signed char>)">; +def pmulhsu_b0_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, unsigned char>)">; +def pmulhsu_b1_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, unsigned char>)">; +def pmulh_h0_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>)">; +def pmulh_h1_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>)">; +def pmulhsu_h0_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, unsigned short>)">; +def pmulhsu_h1_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, unsigned short>)">; + // Packed "Q-format" Multiply Parts Accumulate (32-bit) def mqacc_h00_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; def mqacc_h01_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index f99a05ce673aa..82c69f5d87dcf 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1759,7 +1759,19 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_pmulu_h01_u32x2: case RISCV::BI__builtin_riscv_pmulu_h11_u32x2: case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2: - case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2: { + case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2: + case RISCV::BI__builtin_riscv_pmulh_b0_i16x2: + case RISCV::BI__builtin_riscv_pmulh_b1_i16x2: + case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2: + case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2: + case RISCV::BI__builtin_riscv_pmulh_b0_i16x4: + case RISCV::BI__builtin_riscv_pmulh_b1_i16x4: + case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4: + case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4: + case RISCV::BI__builtin_riscv_pmulh_h0_i32x2: + case RISCV::BI__builtin_riscv_pmulh_h1_i32x2: + case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2: + case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2: { switch (BuiltinID) { default: llvm_unreachable("unexpected builtin ID"); @@ -1803,6 +1815,34 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2: ID = Intrinsic::riscv_pmulsu_11; break; + case RISCV::BI__builtin_riscv_pmulh_b0_i16x2: + case RISCV::BI__builtin_riscv_pmulh_b0_i16x4: + ID = Intrinsic::riscv_pmulh_b0; + break; + case RISCV::BI__builtin_riscv_pmulh_b1_i16x2: + case RISCV::BI__builtin_riscv_pmulh_b1_i16x4: + ID = Intrinsic::riscv_pmulh_b1; + break; + case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2: + case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4: + ID = Intrinsic::riscv_pmulhsu_b0; + break; + case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2: + case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4: + ID = Intrinsic::riscv_pmulhsu_b1; + break; + case RISCV::BI__builtin_riscv_pmulh_h0_i32x2: + ID = Intrinsic::riscv_pmulh_h0; + break; + case RISCV::BI__builtin_riscv_pmulh_h1_i32x2: + ID = Intrinsic::riscv_pmulh_h1; + break; + case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2: + ID = Intrinsic::riscv_pmulhsu_h0; + break; + case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2: + ID = Intrinsic::riscv_pmulhsu_h1; + break; } IntrinsicTypes = {ResultType}; @@ -1867,6 +1907,32 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; } + // Scalar Multiply High Parts + case RISCV::BI__builtin_riscv_mulh_h0_i32: + case RISCV::BI__builtin_riscv_mulh_h1_i32: + case RISCV::BI__builtin_riscv_mulhsu_h0_i32: + case RISCV::BI__builtin_riscv_mulhsu_h1_i32: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_mulh_h0_i32: + ID = Intrinsic::riscv_mulh_h0; + break; + case RISCV::BI__builtin_riscv_mulh_h1_i32: + ID = Intrinsic::riscv_mulh_h1; + break; + case RISCV::BI__builtin_riscv_mulhsu_h0_i32: + ID = Intrinsic::riscv_mulhsu_h0; + break; + case RISCV::BI__builtin_riscv_mulhsu_h1_i32: + ID = Intrinsic::riscv_mulhsu_h1; + break; + } + + IntrinsicTypes = {ResultType, Ops[1]->getType()}; + break; + } + // Packed "Q-format" Multiply Parts Accumulate case RISCV::BI__builtin_riscv_mqacc_h00_i32: case RISCV::BI__builtin_riscv_mqacc_h01_i32: diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index db6d0d37c2e8a..2cee5987c1dac 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -1079,6 +1079,26 @@ __packed_binary_builtin_mixed(mulu_w11_u64, uint64_t, uint32x2_t, uint32x2_t, __ __packed_binary_builtin_mixed(mulsu_w00_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_mulsu_w00_i64) __packed_binary_builtin_mixed(mulsu_w11_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_mulsu_w11_i64) +/* Packed Multiply High Parts (32-bit) */ +__packed_binary_builtin_mixed(pmulh_b0_i16x2, int16x2_t, int16x2_t, int8x4_t, __builtin_riscv_pmulh_b0_i16x2) +__packed_binary_builtin_mixed(pmulh_b1_i16x2, int16x2_t, int16x2_t, int8x4_t, __builtin_riscv_pmulh_b1_i16x2) +__packed_binary_builtin_mixed(pmulhsu_b0_i16x2, int16x2_t, int16x2_t, uint8x4_t, __builtin_riscv_pmulhsu_b0_i16x2) +__packed_binary_builtin_mixed(pmulhsu_b1_i16x2, int16x2_t, int16x2_t, uint8x4_t, __builtin_riscv_pmulhsu_b1_i16x2) +__packed_binary_builtin_mixed(mulh_h0_i32, int32_t, int32_t, int16x2_t, __builtin_riscv_mulh_h0_i32) +__packed_binary_builtin_mixed(mulh_h1_i32, int32_t, int32_t, int16x2_t, __builtin_riscv_mulh_h1_i32) +__packed_binary_builtin_mixed(mulhsu_h0_i32, int32_t, int32_t, uint16x2_t, __builtin_riscv_mulhsu_h0_i32) +__packed_binary_builtin_mixed(mulhsu_h1_i32, int32_t, int32_t, uint16x2_t, __builtin_riscv_mulhsu_h1_i32) + +/* Packed Multiply High Parts (64-bit) */ +__packed_binary_builtin_mixed(pmulh_b0_i16x4, int16x4_t, int16x4_t, int8x8_t, __builtin_riscv_pmulh_b0_i16x4) +__packed_binary_builtin_mixed(pmulh_b1_i16x4, int16x4_t, int16x4_t, int8x8_t, __builtin_riscv_pmulh_b1_i16x4) +__packed_binary_builtin_mixed(pmulhsu_b0_i16x4, int16x4_t, int16x4_t, uint8x8_t, __builtin_riscv_pmulhsu_b0_i16x4) +__packed_binary_builtin_mixed(pmulhsu_b1_i16x4, int16x4_t, int16x4_t, uint8x8_t, __builtin_riscv_pmulhsu_b1_i16x4) +__packed_binary_builtin_mixed(pmulh_h0_i32x2, int32x2_t, int32x2_t, int16x4_t, __builtin_riscv_pmulh_h0_i32x2) +__packed_binary_builtin_mixed(pmulh_h1_i32x2, int32x2_t, int32x2_t, int16x4_t, __builtin_riscv_pmulh_h1_i32x2) +__packed_binary_builtin_mixed(pmulhsu_h0_i32x2, int32x2_t, int32x2_t, uint16x4_t, __builtin_riscv_pmulhsu_h0_i32x2) +__packed_binary_builtin_mixed(pmulhsu_h1_i32x2, int32x2_t, int32x2_t, uint16x4_t, __builtin_riscv_pmulhsu_h1_i32x2) + /* Packed "Q-format" Multiply Parts Accumulate (32-bit) */ __packed_ternary_builtin_cast(mqacc_h00_i32, int, int16x2_t, __builtin_riscv_mqacc_h00_i32) __packed_ternary_builtin_cast(mqacc_h01_i32, int, int16x2_t, __builtin_riscv_mqacc_h01_i32) diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index c6721dbeb5db8..0792df58dbfb4 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -137,7 +137,7 @@ uint64_t test_abs_u64(int64_t a) { /* Packed Splat (32-bit) */ // RV32-LABEL: define dso_local i32 @test_pmv_s_u8x4( -// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] { +// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0 // RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer @@ -145,7 +145,7 @@ uint64_t test_abs_u64(int64_t a) { // RV32-NEXT: ret i32 [[TMP0]] // // RV64-LABEL: define dso_local i32 @test_pmv_s_u8x4( -// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] { +// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0 // RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer @@ -10580,7 +10580,6 @@ uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) { // RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // - int32_t test_mqacc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { return __riscv_mqacc_h00_i32(rd, rs1, rs2); } @@ -10950,6 +10949,346 @@ int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { return __riscv_mqracc_w11_i64(rd, rs1, rs2); } +/* Packed Multiply High Parts (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pmulh_b0_i16x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pmulh_b0_i16x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +int16x2_t test_pmulh_b0_i16x2(int16x2_t rs1, int8x4_t rs2) { + return __riscv_pmulh_b0_i16x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pmulh_b1_i16x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pmulh_b1_i16x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +int16x2_t test_pmulh_b1_i16x2(int16x2_t rs1, int8x4_t rs2) { + return __riscv_pmulh_b1_i16x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +int16x2_t test_pmulhsu_b0_i16x2(int16x2_t rs1, uint8x4_t rs2) { + return __riscv_pmulhsu_b0_i16x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +int16x2_t test_pmulhsu_b1_i16x2(int16x2_t rs1, uint8x4_t rs2) { + return __riscv_pmulhsu_b1_i16x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mulh_h0_i32( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local signext i32 @test_mulh_h0_i32( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV64-NEXT: ret i32 [[TMP1]] +// +int32_t test_mulh_h0_i32(int32_t rs1, int16x2_t rs2) { + return __riscv_mulh_h0_i32(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mulh_h1_i32( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local signext i32 @test_mulh_h1_i32( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV64-NEXT: ret i32 [[TMP1]] +// +int32_t test_mulh_h1_i32(int32_t rs1, int16x2_t rs2) { + return __riscv_mulh_h1_i32(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mulhsu_h0_i32( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local signext i32 @test_mulhsu_h0_i32( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV64-NEXT: ret i32 [[TMP1]] +// +int32_t test_mulhsu_h0_i32(int32_t rs1, uint16x2_t rs2) { + return __riscv_mulhsu_h0_i32(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_mulhsu_h1_i32( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local signext i32 @test_mulhsu_h1_i32( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]]) +// RV64-NEXT: ret i32 [[TMP1]] +// +int32_t test_mulhsu_h1_i32(int32_t rs1, uint16x2_t rs2) { + return __riscv_mulhsu_h1_i32(rs1, rs2); +} + +/* Packed Multiply High Parts (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pmulh_b0_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pmulh_b0_i16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +int16x4_t test_pmulh_b0_i16x4(int16x4_t rs1, int8x8_t rs2) { + return __riscv_pmulh_b0_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pmulh_b1_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV32-NEXT: [[TMP2:%.*]] = cal... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/225015 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
