https://github.com/zeyi2 updated https://github.com/llvm/llvm-project/pull/213431
>From 48f6bcff74d96dd232ee91769330dcd6e154dfa9 Mon Sep 17 00:00:00 2001 From: Zeyi Xu <[email protected]> Date: Sat, 1 Aug 2026 19:05:37 +0800 Subject: [PATCH] [RISCV] Add experimental Smijt, Ssijt, Smehv, and Ssehv support --- .../Driver/print-supported-extensions-riscv.c | 4 ++ .../test/Preprocessor/riscv-target-features.c | 38 +++++++++++++++++++ llvm/docs/RISCVUsage.rst | 2 +- llvm/docs/ReleaseNotes.md | 4 ++ llvm/lib/Target/RISCV/RISCVFeatures.td | 16 ++++++++ llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 + llvm/test/CodeGen/RISCV/attributes.ll | 16 ++++++++ llvm/test/CodeGen/RISCV/features-info.ll | 4 ++ llvm/test/MC/RISCV/attribute-arch.s | 12 ++++++ llvm/test/MC/RISCV/machine-csr-names.s | 14 +++++++ llvm/test/MC/RISCV/supervisor-csr-names.s | 14 +++++++ .../TargetParser/RISCVISAInfoTest.cpp | 4 ++ 12 files changed, 129 insertions(+), 1 deletion(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index c1abb1876d64a..f66e78994bb34 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -271,8 +271,12 @@ // CHECK-NEXT: zvvmttls 0.1 'Zvvmttls' (Transposing Matrix Tile Load/Store) // CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data) // CHECK-NEXT: smcsps 0.19 'Smcsps' (Conditional Stack Pointer Swap at Machine Level) +// CHECK-NEXT: smehv 0.19 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level) +// CHECK-NEXT: smijt 0.19 'Smijt' (Interrupt Jump Table at Machine Level) // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: sscsps 0.19 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level) +// CHECK-NEXT: ssehv 0.19 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level) +// CHECK-NEXT: ssijt 0.19 'Ssijt' (Interrupt Jump Table at Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index d9423ce4baf17..4f2dab85047c0 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -38,7 +38,9 @@ // CHECK-NOT: __riscv_smcsrind {{.*$}} // CHECK-NOT: __riscv_smctr{{.*$}} // CHECK-NOT: __riscv_smdbltrp {{.*$}} +// CHECK-NOT: __riscv_smehv {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} +// CHECK-NOT: __riscv_smijt {{.*$}} // CHECK-NOT: __riscv_smmpm{{.*$}} // CHECK-NOT: __riscv_smnpm{{.*$}} // CHECK-NOT: __riscv_smpmpmt {{.*$}} @@ -53,6 +55,8 @@ // CHECK-NOT: __riscv_sscsrind {{.*$}} // CHECK-NOT: __riscv_ssctr{{.*$}} // CHECK-NOT: __riscv_ssdbltrp {{.*$}} +// CHECK-NOT: __riscv_ssehv {{.*$}} +// CHECK-NOT: __riscv_ssijt {{.*$}} // CHECK-NOT: __riscv_ssnpm{{.*$}} // CHECK-NOT: __riscv_sspm{{.*$}} // CHECK-NOT: __riscv_ssqosid{{.*$}} @@ -1407,6 +1411,40 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_smijt0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMIJT-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_smijt0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMIJT-EXT %s +// CHECK-SMIJT-EXT: __riscv_smijt 19000{{$}} + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssijt0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSIJT-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssijt0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSIJT-EXT %s +// CHECK-SSIJT-EXT: __riscv_ssijt 19000{{$}} + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_smehv0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMEHV-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_smehv0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMEHV-EXT %s +// CHECK-SMEHV-EXT: __riscv_smehv 19000{{$}} +// CHECK-SMEHV-EXT: __riscv_smijt 19000{{$}} + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssehv0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSEHV-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssehv0p19 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSEHV-EXT %s +// CHECK-SSEHV-EXT: __riscv_ssehv 19000{{$}} +// CHECK-SSEHV-EXT: __riscv_ssijt 19000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32ismpmpmt0p6 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPMT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index ab9c007505e9b..201224d190f3a 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -347,7 +347,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__. -``experimental-smcsps``, ``experimental-sscsps`` +``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv`` LLVM implements the `0.19 release specification <https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.19>`__. ``experimental-zvbc32e``, ``experimental-zvkgs`` diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 10b8ede9dbdf7..b84f8b6b60b7d 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -98,6 +98,10 @@ Makes programs 10x faster by doing Special New Thing. * Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer Load) extension. +* Added experimental MC support for the `Smijt` and `Ssijt` interrupt jump + table extensions and the `Smehv` and `Ssehv` synchronous exception hardware + vectoring extensions. + ### Changes to the WebAssembly Backend ### Changes to the Windows Target diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3f48aeb01c641..b3992d951cd51 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1099,6 +1099,22 @@ def FeatureStdExtSsdbltrp def FeatureStdExtSmepmp : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">; +def FeatureStdExtSmijt + : RISCVExperimentalExtension<0, 19, + "Interrupt Jump Table at Machine Level">; +def FeatureStdExtSsijt + : RISCVExperimentalExtension<0, 19, + "Interrupt Jump Table at Supervisor Level">; + +def FeatureStdExtSmehv + : RISCVExperimentalExtension<0, 19, + "Synchronous Exception Hardware Vectoring at Machine Level", + [FeatureStdExtSmijt]>; +def FeatureStdExtSsehv + : RISCVExperimentalExtension<0, 19, + "Synchronous Exception Hardware Vectoring at Supervisor Level", + [FeatureStdExtSsijt]>; + def FeatureStdExtSmpmpmt : RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">; diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 6d9069dc999ec..421a3ae37338d 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -141,6 +141,7 @@ def : SysReg<"sstatus", 0x100>; def : SysReg<"sie", 0x104>; def : SysReg<"stvec", 0x105>; def : SysReg<"scounteren", 0x106>; +def : SysReg<"sijt", 0x107>; def : SysReg<"sieh", 0x114, RV32Only=true>; //===----------------------------------------------------------------------===// @@ -358,6 +359,7 @@ def : SysReg<"mideleg", 0x303>; def : SysReg<"mie", 0x304>; def : SysReg<"mtvec", 0x305>; def : SysReg<"mcounteren", 0x306>; +def : SysReg<"mijt", 0x307>; def : SysReg<"mvien", 0x308>; def : SysReg<"mvip", 0x309>; def : SysReg<"mstatush", 0x310, RV32Only=true>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index e5f1aa0292dd9..48acc224b2819 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -131,6 +131,10 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smcsps %s -o - | FileCheck --check-prefix=RV32SMCSPS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sscsps %s -o - | FileCheck --check-prefix=RV32SSCSPS %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-smijt %s -o - | FileCheck --check-prefix=RV32SMIJT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV32SSIJT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV32SMEHV %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV32SSEHV %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s ; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s @@ -300,6 +304,10 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smcsps %s -o - | FileCheck --check-prefix=RV64SMCSPS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sscsps %s -o - | FileCheck --check-prefix=RV64SSCSPS %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-smijt %s -o - | FileCheck --check-prefix=RV64SMIJT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV64SSIJT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV64SMEHV %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV64SSEHV %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s ; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s @@ -479,6 +487,10 @@ ; RV32SMCSPS: .attribute 5, "rv32i2p1_smcsps0p19" ; RV32SSCSPS: .attribute 5, "rv32i2p1_smcsps0p19_sscsps0p19" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" +; RV32SMIJT: .attribute 5, "rv32i2p1_smijt0p19" +; RV32SSIJT: .attribute 5, "rv32i2p1_ssijt0p19" +; RV32SMEHV: .attribute 5, "rv32i2p1_smehv0p19_smijt0p19" +; RV32SSEHV: .attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19" ; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6" ; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" @@ -645,6 +657,10 @@ ; RV64SMCSPS: .attribute 5, "rv64i2p1_smcsps0p19" ; RV64SSCSPS: .attribute 5, "rv64i2p1_smcsps0p19_sscsps0p19" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" +; RV64SMIJT: .attribute 5, "rv64i2p1_smijt0p19" +; RV64SSIJT: .attribute 5, "rv64i2p1_ssijt0p19" +; RV64SMEHV: .attribute 5, "rv64i2p1_smehv0p19_smijt0p19" +; RV64SSEHV: .attribute 5, "rv64i2p1_ssehv0p19_ssijt0p19" ; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6" ; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index e35240b27509b..febe312db5836 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -25,8 +25,12 @@ ; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)). ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. ; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level). +; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level). +; CHECK-NEXT: experimental-smijt - 'Smijt' (Interrupt Jump Table at Machine Level). ; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: experimental-sscsps - 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level). +; CHECK-NEXT: experimental-ssehv - 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level). +; CHECK-NEXT: experimental-ssijt - 'Ssijt' (Interrupt Jump Table at Supervisor Level). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). ; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 97ca289431a4a..2e68e47e28259 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -363,6 +363,18 @@ .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" +.attribute arch, "rv32i_smijt0p19" +# CHECK: attribute 5, "rv32i2p1_smijt0p19" + +.attribute arch, "rv32i_ssijt0p19" +# CHECK: attribute 5, "rv32i2p1_ssijt0p19" + +.attribute arch, "rv32i_smehv0p19" +# CHECK: attribute 5, "rv32i2p1_smehv0p19_smijt0p19" + +.attribute arch, "rv32i_ssehv0p19" +# CHECK: attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19" + .attribute arch, "rv32i_smpmpmt0p6" # CHECK: attribute 5, "rv32i2p1_smpmpmt0p6" diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index d8a3196af5d44..f115c234a3428 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -187,6 +187,20 @@ csrrs t1, mcounteren, zero # uimm12 csrrs t2, 0x306, zero +# mijt +# name +# CHECK-INST: csrrs t1, mijt, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x30] +# CHECK-INST-ALIAS: csrr t1, mijt +# uimm12 +# CHECK-INST: csrrs t2, mijt, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x30] +# CHECK-INST-ALIAS: csrr t2, mijt +# name +csrrs t1, mijt, zero +# uimm12 +csrrs t2, 0x307, zero + # mscratch # name # CHECK-INST: csrrs t1, mscratch, zero diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s index bf85c7b935be7..07ce581342da8 100644 --- a/llvm/test/MC/RISCV/supervisor-csr-names.s +++ b/llvm/test/MC/RISCV/supervisor-csr-names.s @@ -70,6 +70,20 @@ csrrs t1, scounteren, zero # uimm12 csrrs t2, 0x106, zero +# sijt +# name +# CHECK-INST: csrrs t1, sijt, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x10] +# CHECK-INST-ALIAS: csrr t1, sijt +# uimm12 +# CHECK-INST: csrrs t2, sijt, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x10] +# CHECK-INST-ALIAS: csrr t2, sijt +# name +csrrs t1, sijt, zero +# uimm12 +csrrs t2, 0x107, zero + # stimecmp # name # CHECK-INST: csrrs t1, stimecmp, zero diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 04cbe8b9f661d..02543ff2d18a8 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1661,8 +1661,12 @@ Experimental extensions zvvmttls 0.1 zvzip 0.1 smcsps 0.19 + smehv 0.19 + smijt 0.19 smpmpmt 0.6 sscsps 0.19 + ssehv 0.19 + ssijt 0.19 svukte 0.3 xqccmt 0.1 xsfmclic 0.1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
