================
@@ -1099,6 +1099,22 @@ def FeatureStdExtSsdbltrp
def FeatureStdExtSmepmp
: RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;
+def FeatureStdExtSmijt
+ : RISCVExperimentalExtension<0, 19,
+ "Interrupt Jump Table at Machine Level">;
+def FeatureStdExtSsijt
+ : RISCVExperimentalExtension<0, 19,
+ "Interrupt Jump Table at Supervisor Level">;
+
+def FeatureStdExtSmehv
+ : RISCVExperimentalExtension<0, 19,
+ "Synchronous Exception Hardware Vectoring at
Machine Level",
+ [FeatureStdExtSmijt]>;
----------------
zeyi2 wrote:
The dependency relationships are specified
[here](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L1832-L1835).
The specification does not introduce any new instruction or CSR for these two
extensions. It [adds the `EHV` field to the existing `xijt`
CSR](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L1842-L1849).
and defines how that field changes exception entry behavior. IMO it doesn't
require additional MC instruction or CSR definitions.
I followed the approach used in
[#166322](https://github.com/llvm/llvm-project/pull/166322) to support an
extension with no additional instructions or CSRs.
https://github.com/llvm/llvm-project/pull/213431
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