================
@@ -5457,110 +5448,168 @@ bool
AMDGPUInstructionSelector::selectSBarrierSignalIsfirst(
*MRI);
}
+bool AMDGPUInstructionSelector::selectSGetBarrierState(
+ MachineInstr &I, Intrinsic::ID IntrID) const {
+ MachineBasicBlock *MBB = I.getParent();
+ const DebugLoc &DL = I.getDebugLoc();
+ MachineOperand BarOp = I.getOperand(2);
+ std::optional<int64_t> BarValImm =
+ getIConstantVRegSExtVal(BarOp.getReg(), *MRI);
+
+ if (!BarValImm) {
+ auto CopyMIB = BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
+ .addReg(BarOp.getReg());
+ constrainSelectedInstRegOperands(*CopyMIB, TII, TRI, RBI);
+ }
+ MachineInstrBuilder MIB;
+ unsigned Opc = BarValImm ? AMDGPU::S_GET_BARRIER_STATE_IMM
+ : AMDGPU::S_GET_BARRIER_STATE_M0;
+ MIB = BuildMI(*MBB, &I, DL, TII.get(Opc));
+
+ auto DstReg = I.getOperand(0).getReg();
+ const TargetRegisterClass *DstRC =
+ TRI.getConstrainedRegClassForOperand(I.getOperand(0), *MRI);
+ if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
+ return false;
+ MIB.addDef(DstReg);
+ if (BarValImm) {
+ MIB.addImm(*BarValImm);
+ }
+ I.eraseFromParent();
+ return true;
+}
+
unsigned getNamedBarrierOp(bool HasInlineConst, Intrinsic::ID IntrID) {
if (HasInlineConst) {
switch (IntrID) {
default:
llvm_unreachable("not a named barrier op");
- case Intrinsic::amdgcn_s_barrier_init:
- return AMDGPU::S_BARRIER_INIT_IMM;
case Intrinsic::amdgcn_s_barrier_join:
return AMDGPU::S_BARRIER_JOIN_IMM;
case Intrinsic::amdgcn_s_wakeup_barrier:
return AMDGPU::S_WAKEUP_BARRIER_IMM;
- case Intrinsic::amdgcn_s_get_barrier_state:
+ case Intrinsic::amdgcn_s_get_named_barrier_state:
return AMDGPU::S_GET_BARRIER_STATE_IMM;
};
} else {
switch (IntrID) {
default:
llvm_unreachable("not a named barrier op");
- case Intrinsic::amdgcn_s_barrier_init:
- return AMDGPU::S_BARRIER_INIT_M0;
case Intrinsic::amdgcn_s_barrier_join:
return AMDGPU::S_BARRIER_JOIN_M0;
case Intrinsic::amdgcn_s_wakeup_barrier:
return AMDGPU::S_WAKEUP_BARRIER_M0;
- case Intrinsic::amdgcn_s_get_barrier_state:
+ case Intrinsic::amdgcn_s_get_named_barrier_state:
return AMDGPU::S_GET_BARRIER_STATE_M0;
};
}
}
+bool AMDGPUInstructionSelector::selectNamedBarrierInit(
+ MachineInstr &I, Intrinsic::ID IntrID) const {
+ MachineBasicBlock *MBB = I.getParent();
+ const DebugLoc &DL = I.getDebugLoc();
+ MachineOperand BarOp = I.getOperand(1);
+ MachineOperand CntOp = I.getOperand(2);
+
+ // BarID = (BarOp >> 4) & 0x3F
+ Register TmpReg0 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
+ BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_LSHR_B32), TmpReg0)
+ .add(BarOp)
+ .addImm(4u)
+ .setOperandDead(3); // Dead scc
+
+ Register TmpReg1 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
+ BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_AND_B32), TmpReg1)
+ .addReg(TmpReg0)
+ .addImm(0x3F)
----------------
easyonaadit wrote:
Ditto.
https://github.com/llvm/llvm-project/pull/114550
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