================
@@ -9386,27 +9386,33 @@ SDValue
SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
return DAG.getAtomic(Opcode, SDLoc(Op), M->getMemoryVT(), M->getVTList(),
Ops, M->getMemOperand());
}
- case Intrinsic::amdgcn_s_get_barrier_state: {
+ case Intrinsic::amdgcn_s_get_barrier_state:
+ case Intrinsic::amdgcn_s_get_named_barrier_state: {
SDValue Chain = Op->getOperand(0);
SmallVector<SDValue, 2> Ops;
unsigned Opc;
- bool IsInlinableBarID = false;
- int64_t BarID;
if (isa<ConstantSDNode>(Op->getOperand(2))) {
- BarID = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
- IsInlinableBarID = AMDGPU::isInlinableIntLiteral(BarID);
- }
-
- if (IsInlinableBarID) {
+ uint64_t BarID = cast<ConstantSDNode>(Op->getOperand(2))->getZExtValue();
+ if (IntrID == Intrinsic::amdgcn_s_get_named_barrier_state)
+ BarID = (BarID >> 4) & 0x3F;
Opc = AMDGPU::S_GET_BARRIER_STATE_IMM;
SDValue K = DAG.getTargetConstant(BarID, DL, MVT::i32);
Ops.push_back(K);
Ops.push_back(Chain);
} else {
Opc = AMDGPU::S_GET_BARRIER_STATE_M0;
- SDValue M0Val = copyToM0(DAG, Chain, DL, Op.getOperand(2));
- Ops.push_back(M0Val.getValue(0));
+ if (IntrID == Intrinsic::amdgcn_s_get_named_barrier_state) {
+ SDValue M0Val;
+ M0Val = DAG.getNode(ISD::SRL, DL, MVT::i32, Op->getOperand(2),
+ DAG.getShiftAmountConstant(4, MVT::i32, DL));
+ M0Val = SDValue(
+ DAG.getMachineNode(AMDGPU::S_AND_B32, DL, MVT::i32, M0Val,
+ DAG.getTargetConstant(0x3F, DL, MVT::i32)),
----------------
easyonaadit wrote:
Hi, Are you sure that `0x3F` is the right constant?
Ad defined in `SIDefines.h`:
```
NAMED_BARRIER_FIRST = 1,
NAMED_BARRIER_LAST = 16,
```
That corresponds to 5 bits, so shouldn't it be `0x1F`?
https://github.com/llvm/llvm-project/pull/114550
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