================
@@ -17741,6 +17741,53 @@ void AArch64TargetLowering::getTgtMemIntrinsic(
Infos.push_back(Info);
return;
}
+ case Intrinsic::aarch64_stshh_atomic_store: {
+ const auto *OrderC = dyn_cast<ConstantInt>(I.getArgOperand(2));
+ const auto *SizeC = dyn_cast<ConstantInt>(I.getArgOperand(4));
+ if (!OrderC || !SizeC)
+ return;
+
+ unsigned SizeBits = SizeC->getZExtValue();
+ switch (SizeBits) {
+ case 8:
+ case 16:
+ case 32:
+ case 64:
+ break;
+ default:
+ return;
+ }
+
+ AtomicOrdering Ordering;
+ switch (OrderC->getZExtValue()) {
+ case 0: // __ATOMIC_RELAXED
+ Ordering = AtomicOrdering::Monotonic;
+ break;
+ case 3: // __ATOMIC_RELEASE
+ Ordering = AtomicOrdering::Release;
+ break;
+ case 5: // __ATOMIC_SEQ_CST
+ Ordering = AtomicOrdering::SequentiallyConsistent;
+ break;
+ default:
+ return;
+ }
+
+ // Fill IntrinsicInfo so SelectionDAG builds correctly
+ // typed/aligned atomic store MachineMemOperand.
+ LLVMContext &Ctx = I.getContext();
+ Type *MemTy = IntegerType::get(Ctx, SizeBits);
+ Info.opc = ISD::INTRINSIC_VOID;
+ Info.memVT = EVT::getIntegerVT(Ctx, SizeBits);
+ Info.ptrVal = I.getArgOperand(0);
+ Info.offset = 0;
+ Info.align = DL.getABITypeAlign(MemTy);
+ Info.flags = MachineMemOperand::MOStore;
+ Info.ssid = SyncScope::System;
----------------
jthackray wrote:
It's a synchronisation scope id: system or thread
(`llvm/include/llvm/IR/LLVMContext.h:53`). I'll remove it since it defaults to
System (`llvm/include/llvm/CodeGen/TargetLowering.h:1237`).
https://github.com/llvm/llvm-project/pull/181386
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