================
@@ -1001,6 +1004,72 @@ bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext(
return true;
}
+bool AArch64ExpandPseudo::expandSTSHHAtomicStore(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL(MI.getDebugLoc());
+
+ unsigned Order = MI.getOperand(2).getImm();
+ uint64_t Policy = MI.getOperand(3).getImm();
+ unsigned Size = MI.getOperand(4).getImm();
+
+ bool IsRelaxed = Order == 0;
+ unsigned StoreOpc = 0;
+
+ // __ATOMIC_RELAXED uses STR. __ATOMIC_{RELEASE/SEQ_CST} use STLR.
----------------
jthackray wrote:
https://developer.arm.com/architecture/the-architecture-speaks/?threadId=360cfd76-aa39-47af-88f0-f4aa553d3bb6
says:
```
"Relaxed store: use a normal store (for example STR or other non-Release store
forms) or an atomic instruction variant without release ordering; these do not
introduce the Release ordering described for Store-Release. This follows from
the fact that only Store-Release and release-ordered atomic instructions are
specified to add Release ordering.
Release store: use Store-Release instructions such as STLR, STLRB, STLRH,
STLUR, STLURB, STLURH, or the Exclusive Store-Release forms STLXR, STLXRB,
STLXRH, STLXP, or atomic instructions with release semantics. These are
explicitly defined as Store-Release or release-ordered operations and follow
the Store-Release rules.
Seq_cst store: the architecture states that Load-Acquire and Store-Release
instructions “support the Release Consistency sequentially consistent (RCsc)
model”, so a seq_cst store is implemented using a Store-Release instruction
(for example STLR / STLUR and variants) within an RCsc scheme that also
constrains loads and RMWs appropriately. The manual does not define a separate
“seq_cst store” instruction beyond these Store-Release operations.
All of the above is based on the descriptions of Load-Acquire/Store-Release and
atomic instructions in [B2.6.11 Load-Acquire, Load-AcquirePC, and Store-Release
[L27]](https://developer.arm.com/documentation/ddi0487/maa/170-beihchef),
[C3.2.11 Load-Acquire/Store-Release
[L27]](https://developer.arm.com/documentation/ddi0487/maa/251-chdhfbec), and
[C3.2.17 Atomic instructions
[L27]](https://developer.arm.com/documentation/ddi0487/maa/257-ceghffah)
```
We use `stlr` for the `releasing_store` Pat in AArch64InstrAtomics.td:200 and
plain `str` for `relaxed_store` near there. SEQ_CST store appears to be the
same as release.
https://github.com/llvm/llvm-project/pull/181386
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