https://github.com/MouseSplinter updated https://github.com/llvm/llvm-project/pull/174056
>From 13e11523d1060a4376056fbfa99452c1d27d9df0 Mon Sep 17 00:00:00 2001 From: Wang Yaduo <[email protected]> Date: Tue, 30 Dec 2025 19:16:30 +0800 Subject: [PATCH] [RISCV] Add processor definitions for XuanTie C910V2 and C920V2 XuanTie C910V2 and C920V2 are 64-bit superscalar out-of-order CPUs: https://www.xrvm.com/community/download?id=4530178488929423360 C910V2 is a C920V2 version without vector, zvfbfmin, zvfbfwma, zvfh and xtheadvdot extensions. Scheduling model will be added in a further PR. --- .../riscv-xt-c910v2.c | 73 ++++++++++++++++ .../riscv-xt-c920v2.c | 86 +++++++++++++++++++ clang/test/Driver/riscv-cpus.c | 10 +++ .../test/Misc/target-invalid-cpu-note/riscv.c | 4 + llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVProcessors.td | 50 +++++++++++ 6 files changed, 224 insertions(+) create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-xt-c910v2.c create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-xt-c920v2.c diff --git a/clang/test/Driver/print-enabled-extensions/riscv-xt-c910v2.c b/clang/test/Driver/print-enabled-extensions/riscv-xt-c910v2.c new file mode 100644 index 0000000000000..688b20d3749df --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-xt-c910v2.c @@ -0,0 +1,73 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=xt-c910v2 --print-enabled-extensions | FileCheck %s + +// CHECK: Extensions enabled for the given RISC-V target +// CHECK-EMPTY: +// CHECK-NEXT: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) +// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) +// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) +// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) +// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores) +// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) +// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads) +// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering) +// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero) +// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts) +// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values) +// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode) +// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported) +// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits) +// CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported) +// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) +// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) +// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) +// CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) +// CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) +// CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) +// CHECK-NEXT: xtheadcmo 1.0 'XTHeadCmo' (T-Head cache management instructions) +// CHECK-NEXT: xtheadcondmov 1.0 'XTHeadCondMov' (T-Head conditional move instructions) +// CHECK-NEXT: xtheadfmemidx 1.0 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations) +// CHECK-NEXT: xtheadmac 1.0 'XTHeadMac' (T-Head Multiply-Accumulate Instructions) +// CHECK-NEXT: xtheadmemidx 1.0 'XTHeadMemIdx' (T-Head Indexed Memory Operations) +// CHECK-NEXT: xtheadmempair 1.0 'XTHeadMemPair' (T-Head two-GPR Memory Operations) +// CHECK-NEXT: xtheadsync 1.0 'XTHeadSync' (T-Head multicore synchronization instructions) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_xtheadba1p0_xtheadbb1p0_xtheadbs1p0_xtheadcmo1p0_xtheadcondmov1p0_xtheadfmemidx1p0_xtheadmac1p0_xtheadmemidx1p0_xtheadmempair1p0_xtheadsync1p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-xt-c920v2.c b/clang/test/Driver/print-enabled-extensions/riscv-xt-c920v2.c new file mode 100644 index 0000000000000..006933517dbcd --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-xt-c920v2.c @@ -0,0 +1,86 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=xt-c920v2 --print-enabled-extensions | FileCheck %s + +// CHECK: Extensions enabled for the given RISC-V target +// CHECK-EMPTY: +// CHECK-NEXT: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) +// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) +// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) +// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) +// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) +// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) +// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW) +// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension) +// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension) +// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW) +// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts) +// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add) +// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point) +// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128) +// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32) +// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64) +// CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads) +// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering) +// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero) +// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts) +// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values) +// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode) +// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported) +// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits) +// CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported) +// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) +// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) +// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) +// CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) +// CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) +// CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) +// CHECK-NEXT: xtheadcmo 1.0 'XTHeadCmo' (T-Head cache management instructions) +// CHECK-NEXT: xtheadcondmov 1.0 'XTHeadCondMov' (T-Head conditional move instructions) +// CHECK-NEXT: xtheadfmemidx 1.0 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations) +// CHECK-NEXT: xtheadmac 1.0 'XTHeadMac' (T-Head Multiply-Accumulate Instructions) +// CHECK-NEXT: xtheadmemidx 1.0 'XTHeadMemIdx' (T-Head Indexed Memory Operations) +// CHECK-NEXT: xtheadmempair 1.0 'XTHeadMemPair' (T-Head two-GPR Memory Operations) +// CHECK-NEXT: xtheadsync 1.0 'XTHeadSync' (T-Head multicore synchronization instructions) +// CHECK-NEXT: xtheadvdot 1.0 'XTHeadVdot' (T-Head Vector Extensions for Dot) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zkt1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_xtheadba1p0_xtheadbb1p0_xtheadbs1p0_xtheadcmo1p0_xtheadcondmov1p0_xtheadfmemidx1p0_xtheadmac1p0_xtheadmemidx1p0_xtheadmempair1p0_xtheadsync1p0_xtheadvdot1p0 diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 5d5fdd72baedb..1d0824ba2604c 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -772,3 +772,13 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45mpv | FileCheck -check-prefix=MTUNE-ANDES-AX45MPV %s // MTUNE-ANDES-AX45MPV: "-tune-cpu" "andes-ax45mpv" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xt-c910v2 | FileCheck -check-prefix=MCPU-XT-C910V2 %s +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-xt-c910v2.c` +// MCPU-XT-C910V2: "-target-cpu" "xt-c910v2" +// MCPU-XT-C910V2-SAME: "-target-abi" "lp64d" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xt-c920v2 | FileCheck -check-prefix=MCPU-XT-C920V2 %s +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-xt-c920v2.c` +// MCPU-XT-C920V2: "-target-cpu" "xt-c920v2" +// MCPU-XT-C920V2-SAME: "-target-abi" "lp64d" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 5d6cda0044a99..52b83c10c1f1f 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -56,6 +56,8 @@ // RISCV64-SAME: {{^}}, veyron-v1 // RISCV64-SAME: {{^}}, xiangshan-kunminghu // RISCV64-SAME: {{^}}, xiangshan-nanhu +// RISCV64-SAME: {{^}}, xt-c910v2 +// RISCV64-SAME: {{^}}, xt-c920v2 // RISCV64-SAME: {{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 @@ -117,6 +119,8 @@ // TUNE-RISCV64-SAME: {{^}}, veyron-v1 // TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu +// TUNE-RISCV64-SAME: {{^}}, xt-c910v2 +// TUNE-RISCV64-SAME: {{^}}, xt-c920v2 // TUNE-RISCV64-SAME: {{^}}, andes-45-series // TUNE-RISCV64-SAME: {{^}}, generic // TUNE-RISCV64-SAME: {{^}}, generic-ooo diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 7872e1a9ee551..4ff0dd69e20cb 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -165,6 +165,7 @@ Changes to the RISC-V Backend to be used together when building for the RISC-V platform. * The Xqci Qualcomm uC Vendor Extension is no longer marked as experimental. * The Xqccmp Qualcomm Vendor Extension is no longer marked as experimental. +* `-mcpu=xt-c910v2` and `-mcpu=xt-c920v2` were added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 5becfd2ad502b..cb1ccc11e98fd 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -881,3 +881,53 @@ def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv", FeatureStdExtV, FeatureVendorXAndesPerf], Andes45TuneFeatures>; + +def XUANTIE_C910V2 : RISCVProcessorModel<"xt-c910v2", + GenericOOOModel, + !listconcat(RVB23S64Features, + [FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZca, + FeatureStdExtZcd, + FeatureStdExtZbc, + FeatureVendorXTHeadBa, + FeatureVendorXTHeadBb, + FeatureVendorXTHeadBs, + FeatureVendorXTHeadCmo, + FeatureVendorXTHeadCondMov, + FeatureVendorXTHeadFMemIdx, + FeatureVendorXTHeadMac, + FeatureVendorXTHeadMemIdx, + FeatureVendorXTHeadMemPair, + FeatureVendorXTHeadSync, + FeatureUnalignedScalarMem]), + [TuneVXRMPipelineFlush, + TunePostRAScheduler]>; + +def XUANTIE_C920V2 : RISCVProcessorModel<"xt-c920v2", + GenericOOOModel, + !listconcat( + !listremove(RVB23S64Features, [FeatureStdExtZicclsm]), + [FeatureStdExtV, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZca, + FeatureStdExtZcd, + FeatureStdExtZbc, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureVendorXTHeadBa, + FeatureVendorXTHeadBb, + FeatureVendorXTHeadBs, + FeatureVendorXTHeadCmo, + FeatureVendorXTHeadCondMov, + FeatureVendorXTHeadFMemIdx, + FeatureVendorXTHeadMac, + FeatureVendorXTHeadMemIdx, + FeatureVendorXTHeadMemPair, + FeatureVendorXTHeadSync, + FeatureVendorXTHeadVdot, + FeatureUnalignedScalarMem]), + [TuneVXRMPipelineFlush, + TunePostRAScheduler]>; _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
