================ @@ -1841,6 +1864,48 @@ def INT_NVVM_ADD_RZ_D : F_MATH_2<"add.rz.f64", B64, B64, B64, int_nvvm_add_rz_d> def INT_NVVM_ADD_RM_D : F_MATH_2<"add.rm.f64", B64, B64, B64, int_nvvm_add_rm_d>; def INT_NVVM_ADD_RP_D : F_MATH_2<"add.rp.f64", B64, B64, B64, int_nvvm_add_rp_d>; +// +// Sub +// + +def SUB_RN_SAT_F16_NODE : SDNode<"NVPTXISD::SUB_RN_SAT_F16", SDTFPBinOp>; +def SUB_RN_FTZ_SAT_F16_NODE : + SDNode<"NVPTXISD::SUB_RN_FTZ_SAT_F16", SDTFPBinOp>; +def SUB_RN_SAT_F16X2_NODE : + SDNode<"NVPTXISD::SUB_RN_SAT_F16X2", SDTFPBinOp>; +def SUB_RN_FTZ_SAT_F16X2_NODE : + SDNode<"NVPTXISD::SUB_RN_FTZ_SAT_F16X2", SDTFPBinOp>; + +def INT_NVVM_SUB_RN_SAT_F16 : ---------------- AlexMaclean wrote:
Lets make a class for these 4 patterns. https://github.com/llvm/llvm-project/pull/170079 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
