================ @@ -0,0 +1,39 @@ +// REQUIRES: riscv-registered-target + +// RUN: %clang_cc1 -triple riscv32 -target-feature +v \ +// RUN: -mvscale-min=2 -mvscale-max=2 -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -mvscale-min=2 -mvscale-max=2 -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +// Test RISC-V V-extension fixed-length vector inline assembly constraints. +#include <riscv_vector.h> + +typedef vbool1_t fixed_bool1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); ---------------- topperc wrote:
We should also test this without `riscv_rvv_vector_bits` https://github.com/llvm/llvm-project/pull/150724 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
