[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

[Craig Topper via cfe-commits]

================
@@ -24097,12 +24122,17 @@ SDValue 
RISCVTargetLowering::joinRegisterPartsIntoValue(
     return Val;
   }
 
-  if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
+  if ((ValueVT.isScalableVector() || ValueVT.isFixedLengthVector()) &&
+      PartVT.isScalableVector()) {
     LLVMContext &Context = *DAG.getContext();
     SDValue Val = Parts[0];
     EVT ValueEltVT = ValueVT.getVectorElementType();
     EVT PartEltVT = PartVT.getVectorElementType();
     unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinValue();
+    if (ValueVT.isFixedLengthVector())
+      ValueVTBitSize = getContainerForFixedLengthVector(ValueVT.getSimpleVT())
----------------
topperc wrote:

Why not change ValueVT to the container type before calculating ValueVTBitSize?

https://github.com/llvm/llvm-project/pull/150724
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