llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Paul Walker (paulwalker-arm) <details> <summary>Changes</summary> Feature flags protect instructions not datatypes. This means only builtins associated with +bf16 protected instructions must be guarded. Those that treat the data as opaque 16-bit values (e.g. loads, store and shuffles) should be freely available with the underlying SVE feature. The first commit contains the real work with the second commit only removing "-target-feature +bf16" from RUN lines. The first commit deletes the following files: * clang/test/Sema/aarch64-sve-intrinsics/acle_sve_bfloat.cpp * clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_bfloat.cpp because all the expected diagnostics are not valid behaviour. I don't know why both files do not contain any legitimate +bf16 related builtins so figured they're covered elsewhere or we only cared about the cases when code generation was still possible and so we wanted to ensure we guarantee a compilation failure. --- Patch is 492.02 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/147795.diff 173 Files Affected: - (modified) clang/include/clang/Basic/arm_sve.td (+65-202) - (modified) clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (+14-14) - (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_add-i64.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_mopa-za32.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_mopa-za64.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_mops-za32.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_mops-za64.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (+1-1) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add_sub_za16.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fmlas16.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mopa_nonwide.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret-bfloat.c (+17-17) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-bfloat.c (+6-6) - (modified) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_luti.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_tbl2-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_tbx-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_whilerw-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_whilewr-bfloat.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (+2-2) - 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(modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ldnt1.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pext.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (+3-3) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_psel.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_psel_svcount.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ptrue.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (+10-10) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (+7-7) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_stnt1.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (+5-5) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_pn.c (+2-2) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (+4-4) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (+8-8) - (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (+8-8) - (removed) clang/test/Sema/aarch64-sve-intrinsics/acle_sve_bfloat.cpp (-87) - (removed) clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_bfloat.cpp (-29) ``````````diff diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index f0a8b32bf2f88..b4b94b8816d48 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -19,7 +19,7 @@ include "arm_sve_sme_incl.td" // Loads // Load one vector (scalar base) -def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfdm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ld1">; +def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfdbm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ld1">; def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl", [IsLoad, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_ld1">; def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_ld1">; def SVLD1SH : MInst<"svld1sh_{d}", "dPT", "ilUiUl", [IsLoad, VerifyRuntimeMode], MemEltTyInt16, "aarch64_sve_ld1">; @@ -27,13 +27,8 @@ def SVLD1UH : MInst<"svld1uh_{d}", "dPX", "ilUiUl", [IsLoad, IsZExtRetu def SVLD1SW : MInst<"svld1sw_{d}", "dPU", "lUl", [IsLoad, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_ld1">; def SVLD1UW : MInst<"svld1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_ld1">; -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVLD1_BF : MInst<"svld1[_{2}]", "dPc", "b", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ld1">; - def SVLD1_VNUM_BF : MInst<"svld1_vnum[_{2}]", "dPcl", "b", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ld1">; -} - // Load one vector (scalar base, VL displacement) -def SVLD1_VNUM : MInst<"svld1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ld1">; +def SVLD1_VNUM : MInst<"svld1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdbm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ld1">; def SVLD1SB_VNUM : MInst<"svld1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_ld1">; def SVLD1UB_VNUM : MInst<"svld1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_ld1">; def SVLD1SH_VNUM : MInst<"svld1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad, VerifyRuntimeMode], MemEltTyInt16, "aarch64_sve_ld1">; @@ -121,7 +116,7 @@ def SVLD1UW_GATHER_INDEX_S : MInst<"svld1uw_gather[_{2}base]_index_{d}", "dPul // First-faulting load one vector (scalar base) -def SVLDFF1 : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; +def SVLDFF1 : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfdbm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; def SVLDFF1SB : MInst<"svldff1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldff1">; def SVLDFF1UB : MInst<"svldff1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1">; def SVLDFF1SH : MInst<"svldff1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldff1">; @@ -130,7 +125,7 @@ def SVLDFF1SW : MInst<"svldff1sw_{d}", "dPU", "lUl", [IsLoad], def SVLDFF1UW : MInst<"svldff1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1">; // First-faulting load one vector (scalar base, VL displacement) -def SVLDFF1_VNUM : MInst<"svldff1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; +def SVLDFF1_VNUM : MInst<"svldff1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdbm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; def SVLDFF1SB_VNUM : MInst<"svldff1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldff1">; def SVLDFF1UB_VNUM : MInst<"svldff1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1">; def SVLDFF1SH_VNUM : MInst<"svldff1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldff1">; @@ -139,11 +134,6 @@ def SVLDFF1SW_VNUM : MInst<"svldff1sw_vnum_{d}", "dPUl", "lUl", [IsL def SVLDFF1UW_VNUM : MInst<"svldff1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1">; } // let SVETargetGuard = "sve", SMETargetGuard = InvalidMode -let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in { - def SVLDFF1_BF : MInst<"svldff1[_{2}]", "dPc", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; - def SVLDFF1_VNUM_BF : MInst<"svldff1_vnum[_{2}]", "dPcl", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; -} - let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { // First-faulting load one vector (vector base) def SVLDFF1_GATHER_BASES_U : MInst<"svldff1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_scalar_offset">; @@ -223,7 +213,7 @@ def SVLDFF1SW_GATHER_INDEX_S : MInst<"svldff1sw_gather[_{2}base]_index_{d}", "dP def SVLDFF1UW_GATHER_INDEX_S : MInst<"svldff1uw_gather[_{2}base]_index_{d}", "dPul", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; // Non-faulting load one vector (scalar base) -def SVLDNF1 : MInst<"svldnf1[_{2}]", "dPc", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; +def SVLDNF1 : MInst<"svldnf1[_{2}]", "dPc", "csilUcUsUiUlhfdbm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; def SVLDNF1SB : MInst<"svldnf1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldnf1">; def SVLDNF1UB : MInst<"svldnf1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnf1">; def SVLDNF1SH : MInst<"svldnf1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldnf1">; @@ -232,7 +222,7 @@ def SVLDNF1SW : MInst<"svldnf1sw_{d}", "dPU", "lUl", [IsLoad], def SVLDNF1UW : MInst<"svldnf1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnf1">; // Non-faulting load one vector (scalar base, VL displacement) -def SVLDNF1_VNUM : MInst<"svldnf1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; +def SVLDNF1_VNUM : MInst<"svldnf1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdbm", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; def SVLDNF1SB_VNUM : MInst<"svldnf1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldnf1">; def SVLDNF1UB_VNUM : MInst<"svldnf1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnf1">; def SVLDNF1SH_VNUM : MInst<"svldnf1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ldnf1">; @@ -241,34 +231,17 @@ def SVLDNF1SW_VNUM : MInst<"svldnf1sw_vnum_{d}", "dPUl", "lUl", [IsL def SVLDNF1UW_VNUM : MInst<"svldnf1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnf1">; } // let SVETargetGuard = "sve", SMETargetGuard = InvalidMode -let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in { - def SVLDNF1_BF : MInst<"svldnf1[_{2}]", "dPc", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; - def SVLDNF1_VNUM_BF : MInst<"svldnf1_vnum[_{2}]", "dPcl", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; -} - // Load one vector, unextended load, non-temporal (scalar base) -def SVLDNT1 : MInst<"svldnt1[_{2}]", "dPc", "csilUcUsUiUlhfdm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ldnt1">; +def SVLDNT1 : MInst<"svldnt1[_{2}]", "dPc", "csilUcUsUiUlhfdbm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ldnt1">; // Load one vector, unextended load, non-temporal (scalar base, VL displacement) -def SVLDNT1_VNUM : MInst<"svldnt1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ldnt1">; - -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVLDNT1_BF : MInst<"svldnt1[_{2}]", "dPc", "b", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ldnt1">; - def SVLDNT1_VNUM_BF : MInst<"svldnt1_vnum[_{2}]", "dPcl", "b", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ldnt1">; -} +def SVLDNT1_VNUM : MInst<"svldnt1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfdbm", [IsLoad, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_ldnt1">; // Load one quadword and replicate (scalar base) -def SVLD1RQ : SInst<"svld1rq[_{2}]", "dPc", "csilUcUsUiUlhfdm", MergeNone, "aarch64_sve_ld1rq", [VerifyRuntimeMode]>; - -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc", "b", MergeNone, "aarch64_sve_ld1rq", [VerifyRuntimeMode]>; -} +def SVLD1RQ : SInst<"svld1rq[_{2}]", "dPc", "csilUcUsUiUlhfdbm", MergeNone, "aarch64_sve_ld1rq", [VerifyRuntimeMode]>; multiclass StructLoad<string name, string proto, string i, list<FlagType> f = []> { - def : SInst<name, proto, "csilUcUsUiUlhfdm", MergeNone, i, !listconcat(f, [IsStructLoad])>; - let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def: SInst<name, proto, "b", MergeNone, i, !listconcat(f, [IsStructLoad])>; - } + def : SInst<name, proto, "csilUcUsUiUlhfdbm", MergeNone, i, !listconcat(f, [IsStructLoad])>; } // Load N-element structure into N vectors (scalar base) @@ -283,10 +256,7 @@ defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", "aarch64_sve_ld4_sret", // Load one octoword and replicate (scalar base) let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in { - def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfdm", MergeNone, "aarch64_sve_ld1ro">; -} -let SVETargetGuard = "sve,f64mm,bf16", SMETargetGuard = InvalidMode in { - def SVLD1RO_BF16 : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, "aarch64_sve_ld1ro">; + def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfdbm", MergeNone, "aarch64_sve_ld1ro">; } let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in { @@ -343,7 +313,7 @@ let SVETargetGuard = "sve2p1|sme2p1", SMETargetGuard = "sve2p1|sme2p1" in { // Stores // Store one vector (scalar base) -def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfdm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_st1">; +def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfdbm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_st1">; def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_st1">; def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_st1">; def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore, VerifyRuntimeMode], MemEltTyInt16, "aarch64_sve_st1">; @@ -352,7 +322,7 @@ def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore, Verify def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_st1">; // Store one vector (scalar base, VL displacement) -def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfdm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_st1">; +def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfdbm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_st1">; def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_st1">; def SVST1B_VNUM_U : MInst<"svst1b_vnum[_{d}]", "vPEld", "UsUiUl", [IsStore, VerifyRuntimeMode], MemEltTyInt8, "aarch64_sve_st1">; def SVST1H_VNUM_S : MInst<"svst1h_vnum[_{d}]", "vPBld", "il", [IsStore, VerifyRuntimeMode], MemEltTyInt16, "aarch64_sve_st1">; @@ -360,11 +330,6 @@ def SVST1H_VNUM_U : MInst<"svst1h_vnum[_{d}]", "vPFld", "UiUl", [IsSt def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l", [IsStore, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_st1">; def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul", [IsStore, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_st1">; -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVST1_BF : MInst<"svst1[_{d}]", "vPpd", "b", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_st1">; - def SVST1_VNUM_BF : MInst<"svst1_vnum[_{d}]", "vPpld", "b", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_st1">; -} - let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { // Store one vector (vector base) def SVST1_SCATTER_BASES_U : MInst<"svst1_scatter[_{2}base_{d}]", "vPud", "ilUiUlfd", [IsScatterStore], MemEltTyDefault, "aarch64_sve_st1_scatter_scalar_offset">; @@ -437,11 +402,9 @@ def SVST1W_SCATTER_INDEX_S : MInst<"svst1w_scatter[_{2}base]_index[_{d}]", "v } // let SVETargetGuard = "sve" multiclass StructStore<string name, string proto, string i, list<FlagType> f = []> { - def : SInst<name, proto, "csilUcUsUiUlhfdm", MergeNone, i, !listconcat(f, [IsStructStore])>; - let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def: SInst<name, proto, "b", MergeNone, i, !listconcat(f, [IsStructStore])>; - } + def : SInst<name, proto, "csilUcUsUiUlhfdbm", MergeNone, i, !listconcat(f, [IsStructStore])>; } + // Store N vectors into N-element structure (scalar base) defm SVST2 : StructStore<"svst2[_{d}]", "vPp2", "aarch64_sve_st2", [VerifyRuntimeMode]>; defm SVST3 : StructStore<"svst3[_{d}]", "vPp3", "aarch64_sve_st3", [VerifyRuntimeMode]>; @@ -453,15 +416,10 @@ defm SVST3_VNUM : StructStore<"svst3_vnum[_{d}]", "vPpl3", "aarch64_sve_st3", [V defm SVST4_VNUM : StructStore<"svst4_vnum[_{d}]", "vPpl4", "aarch64_sve_st4", [VerifyRuntimeMode]>; // Store one vector, with no truncation, non-temporal (scalar base) -def SVSTNT1 : MInst<"svstnt1[_{d}]", "vPpd", "csilUcUsUiUlhfdm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_stnt1">; +def SVSTNT1 : MInst<"svstnt1[_{d}]", "vPpd", "csilUcUsUiUlhfdbm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_stnt1">; // Store one vector, with no truncation, non-temporal (scalar base, VL displacement) -def SVSTNT1_VNUM : MInst<"svstnt1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfdm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_stnt1">; - -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVSTNT1_BF : MInst<"svstnt1[_{d}]", "vPpd", "b", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_stnt1">; - def SVSTNT1_VNUM_BF : MInst<"svstnt1_vnum[_{d}]", "vPpld", "b", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_stnt1">; -} +def SVSTNT1_VNUM : MInst<"svstnt1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfdbm", [IsStore, VerifyRuntimeMode], MemEltTyDefault, "aarch64_sve_stnt1">; let SVETargetGuard = "sve2p1", SMETargetGuard = InvalidMode in { // Contiguous truncating store from quadword (single vector). @@ -563,18 +521,12 @@ def SVADRD : SInst<"svadrd[_{0}base]_[{2}]index", "uud", "ilUiUl", MergeNone, " // Scalar to vector def SVDUPQ_8 : SInst<"svdupq[_n]_{d}", "dssssssssssssssss", "cUc", MergeNone, "", [VerifyRuntimeMode]>; -def SVDUPQ_16 : SInst<"svdupq[_n]_{d}", "dssssssss", "sUsh", MergeNone, "", [VerifyRuntimeMode]>; -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVDUPQ_BF16 : SInst<"svdupq[_n]_{d}", "dssssssss", "b", MergeNone, "", [VerifyRuntimeMode]>; -} +def SVDUPQ_16 : SInst<"svdupq[_n]_{d}", "dssssssss", "sUshb", MergeNone, "", [VerifyRuntimeMode]>; def SVDUPQ_32 : SInst<"svdupq[_n]_{d}", "dssss", "iUif", MergeNone, "", [VerifyRuntimeMode]>; def SVDUPQ_64 : SInst<"svdupq[_n]_{d}", "dss", "lUld", MergeNone, "", [VerifyRuntimeMode]>; multiclass svdup_base<string n, string p, MergeType mt, string i> { - def NAME : SInst<n, p, "csilUcUsUiUlhfd", mt, i, [VerifyRuntimeMode]>; - let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def _BF16: SInst<n, p, "b", mt, i, [VerifyRuntimeMode]>; - } + def NAME : SInst<n, p, "csilUcUsUiUlhfdb", mt, i, [VerifyRuntimeMode]>; } defm SVDUP : svdup_base<"svdup[_n]_{d}", "ds", MergeNone, "aarch64_sve_dup_x">; @@ -700,10 +652,7 @@ def SVASRD_M : SInst<"svasrd[_n_{d}]", "dPdi", "csil", MergeOp1, "aa def SVASRD_X : SInst<"svasrd[_n_{d}]", "dPdi", "csil", MergeAny, "aarch64_sve_asrd", [VerifyRuntimeMode], [ImmCheck<2, ImmCheckShiftRight, 1>]>; def SVASRD_Z : SInst<"svasrd[_n_{d}]", "dPdi", "csil", MergeZero, "aarch64_sve_asrd", [VerifyRuntimeMode], [ImmCheck<2, ImmCheckShiftRight, 1>]>; -def SVINSR : SInst<"svinsr[_n_{d}]", "dds", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_insr", [VerifyRuntimeMode]>; -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVINSR_BF16 : SInst<"svinsr[_n_{d}]", "dds", "b", MergeNone, "aarch64_sve_insr", [VerifyRuntimeMode]>; -} +def SVINSR : SInst<"svinsr[_n_{d}]", "dds", "csilUcUsUiUlhfdb", MergeNone, "aarch64_sve_insr", [VerifyRuntimeMode]>; //////////////////////////////////////////////////////////////////////////////// // Integer reductions @@ -786,13 +735,9 @@ multiclass SInstCLS<string name, string types, string intrinsic, list<FlagType> def _Z : SInst<name # "[_{d}]", "uPd", types, MergeZeroExp, intrinsic, flags>; } -defm SVCLS : SInstCLS<"svcls", "csil", "aarch64_sve_cls", [VerifyRuntimeMode]>; -defm SVCLZ : SInstCLS<"svclz", "csilUcUsUiUl", "aarch64_sve_clz", [VerifyRuntimeMode]>; -defm SVCNT : SInstCLS<"svcnt", "csilUcUsUiUlhfd", "aarch64_sve_cnt", [VerifyRuntimeMode]>; - -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - defm SVCNT_BF16 : SInstCLS<"svcnt", "b", "aarch64_sve_cnt", [VerifyRuntimeMode]>; -} +defm SVCLS : SInstCLS<"svcls", "csil", "aarch64_sve_cls", [VerifyRuntimeMode]>; +defm SVCLZ : SInstCLS<"svclz", "csilUcUsUiUl", "aarch64_sve_clz", [VerifyRuntimeMode]>; +defm SVCNT : SInstCLS<"svcnt", "csilUcUsUiUlhfdb", "aarch64_sve_cnt", [VerifyRuntimeMode]>; //////////////////////////////////////////////////////////////////////////////// // Conversion @@ -1034,10 +979,7 @@ def SVCVTXNT_F32_F64 : SInst<"svcvtxnt_f32[_f64]", "MMPd", "d", MergeOp1, "aar // Permutations and selection multiclass SVEPerm<string name, string proto, string i> { - def : SInst<name, proto, "csilUcUsUiUlhfd", MergeNone, i, [VerifyRuntimeMode]>; - let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def: SInst<name, proto, "b", MergeNone, i, [VerifyRuntimeMode]>; - } + def : SInst<name, proto, "csilUcUsUiUlhfdb", MergeNone, i, [VerifyRuntimeMode]>; } defm SVCLASTA : SVEPerm<"svclasta[_{d}]", "dPdd", "aarch64_sve_clasta">; @@ -1053,51 +995,26 @@ def SVCOMPACT : SInst<"svcompact[_{d}]", "dPd", "ilUiUlfd", MergeNo // splat of any possible lane. It is upto LLVM to pick a more efficient // instruction such as DUP (indexed) if the lane index fits the range of the // instruction's immediate. -def SVDUP_LANE : SInst<"svdup_lane[_{d}]", "ddL", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_tbl", [VerifyRuntimeMode]>; -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { -def SVDUP_LANE_BF16 : - SInst<"svdup_lane[_{d}]", "ddL", "b", MergeNone, "aarch64_sve_tbl", [VerifyRuntimeMode]>; -} - -def SVDUPQ_LANE : SInst<"svdupq_lane[_{d}]", "ddn", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_dupq_lane", [VerifyRuntimeMode]>; -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { - def SVDUPQ_LANE_BF16 : SInst<"svdupq_lane[_{d}]", "ddn", "b", MergeNone, "aarch64_sve_dupq_lane", [VerifyRuntimeMode]>; -} -def SVEXT : SInst<"svext[_{d}]", "dddi", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ext", [VerifyRuntimeMode], [ImmCheck<2, ImmCheckExtract, 1>]>; +def SVDUP_LANE : SInst<"svdup_lan... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/147795 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
