Author: Elvina Yakubova Date: 2025-07-09T11:43:08+01:00 New Revision: 69835d8f6d5b343306fbbb401af85fdd891be794
URL: https://github.com/llvm/llvm-project/commit/69835d8f6d5b343306fbbb401af85fdd891be794 DIFF: https://github.com/llvm/llvm-project/commit/69835d8f6d5b343306fbbb401af85fdd891be794.diff LOG: [clang][AArch64] Parse more features in getHostCPUFeatures (#146323) Add parsing of some crypto features to display them properly when -mcpu=native is used Added: clang/test/Driver/Inputs/cpunative/grace Modified: clang/test/Driver/aarch64-mcpu-native.c clang/test/Driver/print-enabled-extensions/aarch64-grace.c llvm/lib/TargetParser/Host.cpp Removed: clang/test/Driver/Inputs/cpunative/neoverse-v2 ################################################################################ diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-v2 b/clang/test/Driver/Inputs/cpunative/grace similarity index 100% rename from clang/test/Driver/Inputs/cpunative/neoverse-v2 rename to clang/test/Driver/Inputs/cpunative/grace diff --git a/clang/test/Driver/aarch64-mcpu-native.c b/clang/test/Driver/aarch64-mcpu-native.c index a349a8e9827b8..db410bf1e000d 100644 --- a/clang/test/Driver/aarch64-mcpu-native.c +++ b/clang/test/Driver/aarch64-mcpu-native.c @@ -1,63 +1,4 @@ // REQUIRES: aarch64-registered-target,system-linux,aarch64-host -// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/neoverse-v2 -// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-NV2 --implicit-check-not=FEAT_ %s - -// CHECK-FEAT-NV2: Extensions enabled for the given AArch64 target -// CHECK-FEAT-NV2-EMPTY: -// CHECK-FEAT-NV2: Architecture Feature(s) Description -// CHECK-FEAT-NV2: FEAT_AES, FEAT_PMULL Enable AES support -// CHECK-FEAT-NV2: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension -// CHECK-FEAT-NV2: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-FEAT-NV2: FEAT_BF16 Enable BFloat16 Extension -// CHECK-FEAT-NV2: FEAT_BTI Enable Branch Target Identification -// CHECK-FEAT-NV2: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets -// CHECK-FEAT-NV2: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions -// CHECK-FEAT-NV2: FEAT_CSV2_2 Enable architectural speculation restriction -// CHECK-FEAT-NV2: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions -// CHECK-FEAT-NV2: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence -// CHECK-FEAT-NV2: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence -// CHECK-FEAT-NV2: FEAT_DotProd Enable dot product support -// CHECK-FEAT-NV2: FEAT_ETE Enable Embedded Trace Extension -// CHECK-FEAT-NV2: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support -// CHECK-FEAT-NV2: FEAT_FHM Enable FP16 FML instructions -// CHECK-FEAT-NV2: FEAT_FP Enable Armv8.0-A Floating Point Extensions -// CHECK-FEAT-NV2: FEAT_FP16 Enable half-precision floating-point data processing -// CHECK-FEAT-NV2: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement -// CHECK-FEAT-NV2: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int -// CHECK-FEAT-NV2: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions -// CHECK-FEAT-NV2: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons -// CHECK-FEAT-NV2: FEAT_I8MM Enable Matrix Multiply Int8 Extension -// CHECK-FEAT-NV2: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions -// CHECK-FEAT-NV2: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension -// CHECK-FEAT-NV2: FEAT_LRCPC Enable support for RCPC extension -// CHECK-FEAT-NV2: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets -// CHECK-FEAT-NV2: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions -// CHECK-FEAT-NV2: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules -// CHECK-FEAT-NV2: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension -// CHECK-FEAT-NV2: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension -// CHECK-FEAT-NV2: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement -// CHECK-FEAT-NV2: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension -// CHECK-FEAT-NV2: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants -// CHECK-FEAT-NV2: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension -// CHECK-FEAT-NV2: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension -// CHECK-FEAT-NV2: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions -// CHECK-FEAT-NV2: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions -// CHECK-FEAT-NV2: FEAT_RNG Enable Random Number generation instructions -// CHECK-FEAT-NV2: FEAT_SB Enable Armv8.5-A Speculation Barrier -// CHECK-FEAT-NV2: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension -// CHECK-FEAT-NV2: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support -// CHECK-FEAT-NV2: FEAT_SPE Enable Statistical Profiling extension -// CHECK-FEAT-NV2: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions -// CHECK-FEAT-NV2: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit -// CHECK-FEAT-NV2: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions -// CHECK-FEAT-NV2: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions -// CHECK-FEAT-NV2: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions -// CHECK-FEAT-NV2: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions -// CHECK-FEAT-NV2: FEAT_TRBE Enable Trace Buffer Extension -// CHECK-FEAT-NV2: FEAT_TRF Enable Armv8.4-A Trace extension -// CHECK-FEAT-NV2: FEAT_UAO Enable Armv8.2-A UAO PState -// CHECK-FEAT-NV2: FEAT_VHE Enable Armv8.1-A Virtual Host extension - // RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/neoverse-n1 // RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-NN1 --implicit-check-not=FEAT_ %s diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c index 78d991c3ab184..b66e649965489 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c @@ -1,5 +1,6 @@ -// REQUIRES: aarch64-registered-target +// REQUIRES: aarch64-registered-target,aarch64-host,system-linux // RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s +// RUN: env LLVM_CPUINFO=%S/../Inputs/cpunative/grace %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s // CHECK: Extensions enabled for the given AArch64 target // CHECK-EMPTY: diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 3b80c152c1264..8fd91fcd33f63 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -2100,8 +2100,13 @@ const StringMap<bool> sys::getHostCPUFeatures() { .Case("fp", "fp-armv8") .Case("crc32", "crc") .Case("atomics", "lse") + .Case("sha3", "sha3") + .Case("sm4", "sm4") .Case("sve", "sve") .Case("sve2", "sve2") + .Case("sveaes", "sve-aes") + .Case("svesha3", "sve-sha3") + .Case("svesm4", "sve-sm4") #else .Case("half", "fp16") .Case("neon", "neon") _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
