================ @@ -462,6 +474,12 @@ def FPR64C : RISCVRegisterClass<[f64], 64, (add (sequence "F%u_D", 8, 9) )>; +def FPR128 : RISCVRegisterClass< + [f128], 128, ---------------- topperc wrote:
Format this the same was as FPR64? https://github.com/llvm/llvm-project/pull/139369 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
