================
@@ -215,17 +342,115 @@ void sw9(int a) {
// OGCG: entry:
// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4
// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4
-// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [
+// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [
// OGCG: i32 3, label %[[SW3:.*]]
// OGCG: i32 4, label %[[SW4:.*]]
// OGCG: ]
// OGCG: [[SW3]]:
-// OGCG: br label %[[EPILOG]]
+// OGCG: br label %[[EPILOG:.*]]
+// OGCG: [[DEFAULT]]:
+// OGCG: br label %[[SW4]]
// OGCG: [[SW4]]:
// OGCG: br label %[[EPILOG]]
// OGCG: [[EPILOG]]:
// OGCG: ret void
+void sw10(int a) {
+ switch (a)
+ {
+ case 3:
+ break;
+ case 4:
+ default:
+ case 5:
+ break;
+ }
+}
+
+//CIR: cir.func @_Z4sw10i
+//CIR: cir.case(equal, [#cir.int<3> : !s32i]) {
+//CIR-NEXT: cir.break
+//CIR-NEXT: }
+//CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) {
+//CIR-NEXT: cir.yield
+//CIR-NEXT: }
+//CIR-NEXT: cir.case(default, []) {
+//CIR-NEXT: cir.yield
+//CIR-NEXT: }
+//CIR-NEXT: cir.case(equal, [#cir.int<5> : !s32i]) {
+//CIR-NEXT: cir.break
+//CIR-NEXT: }
+
+// OGCG: define dso_local void @_Z4sw10i
+// OGCG: entry:
+// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4
+// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4
+// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [
+// OGCG: i32 3, label %[[BB3:.*]]
+// OGCG: i32 4, label %[[BB4:.*]]
+// OGCG: i32 5, label %[[BB5:.*]]
+// OGCG: ]
+// OGCG: [[BB3]]:
+// OGCG: br label %[[EPILOG:.*]]
+// OGCG: [[BB4]]:
+// OGCG: br label %[[DEFAULT]]
+// OGCG: [[DEFAULT]]:
+// OGCG: br label %[[BB5]]
+// OGCG: [[BB5]]:
+// OGCG: br label %[[EPILOG]]
+// OGCG: [[EPILOG]]:
+// OGCG: ret void
+
+void sw11(int a) {
+ switch (a)
+ {
+ case 3:
+ break;
+ case 4:
+ case 5:
+ default:
+ case 6:
+ case 7:
+ break;
+ }
+}
+
+//CIR: cir.func @_Z4sw11i
+//CIR: cir.case(equal, [#cir.int<3> : !s32i]) {
+//CIR-NEXT: cir.break
+//CIR-NEXT: }
+//CIR-NEXT: cir.case(anyof, [#cir.int<4> : !s32i, #cir.int<5> : !s32i]) {
+//CIR-NEXT: cir.yield
+//CIR-NEXT: }
+//CIR-NEXT: cir.case(default, []) {
+//CIR-NEXT: cir.yield
+//CIR-NEXT: }
+//CIR-NEXT: cir.case(anyof, [#cir.int<6> : !s32i, #cir.int<7> : !s32i]) {
+//CIR-NEXT: cir.break
+//CIR-NEXT: }
+
+// OGCG: define dso_local void @_Z4sw11i
+// OGCG: entry:
+// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4
+// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4
+// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [
+// OGCG: i32 3, label %[[BB3:.*]]
+// OGCG: i32 4, label %[[BB4:.*]]
+// OGCG: i32 5, label %[[BB4]]
+// OGCG: i32 6, label %[[BB6:.*]]
+// OGCG: i32 7, label %[[BB6]]
+// OGCG: ]
+// OGCG: [[BB3]]:
+// OGCG: br label %[[EPILOG:.*]]
+// OGCG: [[BB4]]:
+// OGCG: br label %[[DEFAULT]]
+// OGCG: [[DEFAULT]]:
+// OGCG: br label %[[BB6]]
+// OGCG: [[BB6]]:
+// OGCG: br label %[[EPILOG]]
+// OGCG: [[EPILOG]]:
+// OGCG: ret void
+
----------------
andykaylor wrote:
Can you add a test that has non-break statements between cases?
```
void f(int x) {
int y;
switch (x) {
case 1:
case 2:
y = 0;
case 3:
break;
default:
break;
}
}
```
https://github.com/llvm/llvm-project/pull/138003
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