================
@@ -3107,6 +3107,23 @@ let TargetPrefix = "aarch64" in {
}
}
+ class SME_OuterProduct_TMOP_Intrinsic
+ : DefaultAttrsIntrinsic<[],
+ [llvm_i32_ty,
+ llvm_anyvector_ty,
+ LLVMMatchType<0>,
+ LLVMMatchType<0>,
+ llvm_nxv16i8_ty,
+ llvm_i32_ty],
+ [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<5>>,
+ IntrInaccessibleMemOnly]>;
+
+ def int_aarch64_sme_tmopa : SME_OuterProduct_TMOP_Intrinsic;
----------------
CarolineConcatto wrote:
We will also need to have different llvm-ir for FP8 because its properties is
different from the non-fp8.
Fp8 llvm-ir needs to have: IntrInaccessibleMemOnly, IntrHasSideEffects
And the SME_OuterProduct_TMOP_Intrinsic, should only have: IntrNoMem,
IntrHasSideEffects
The attribute IntrInaccessibleMemOnly is only needed in the FP8 because of FPMR
register
https://github.com/llvm/llvm-project/pull/135145
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