https://github.com/futog updated
https://github.com/llvm/llvm-project/pull/130286
>From ef22b36c6aa53566554b0f58bd2b90432f9a5f5a Mon Sep 17 00:00:00 2001
From: Gergely Futo <gergely.f...@hightec-rt.com>
Date: Thu, 10 Oct 2024 08:36:50 +0200
Subject: [PATCH] [libunwind][RISCV] Make asm statement volatile
Compiling with `O3`, the `early-machinelicm` pass hoisted the asm
statement to a path that has been executed unconditionally during
stack unwinding. On hardware without vector extension support, this
resulted in reading a nonexistent register.
---
libunwind/src/Registers.hpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp
index 452f46a0d56ea..2c3bfb7e8428a 100644
--- a/libunwind/src/Registers.hpp
+++ b/libunwind/src/Registers.hpp
@@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum)
const {
return _registers[regNum];
if (regNum == UNW_RISCV_VLENB) {
reg_t vlenb;
- __asm__("csrr %0, 0xC22" : "=r"(vlenb));
+ __asm__ volatile("csrr %0, 0xC22" : "=r"(vlenb));
return vlenb;
}
_LIBUNWIND_ABORT("unsupported riscv register");
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