llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-libunwind Author: Gergely Futo (futog) <details> <summary>Changes</summary> Compiling with `O3`, the `early-machinelicm` pass hoisted the asm statement to a path that has been executed unconditionally during stack unwinding. On hardware without vector extension support, this resulted in reading a nonexistent register. --- Full diff: https://github.com/llvm/llvm-project/pull/130286.diff 1 Files Affected: - (modified) libunwind/src/Registers.hpp (+1-1) ``````````diff diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp index 452f46a0d56ea..3b28874c9ae32 100644 --- a/libunwind/src/Registers.hpp +++ b/libunwind/src/Registers.hpp @@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const { return _registers[regNum]; if (regNum == UNW_RISCV_VLENB) { reg_t vlenb; - __asm__("csrr %0, 0xC22" : "=r"(vlenb)); + __asm__ volatile ("csrr %0, 0xC22" : "=r"(vlenb)); return vlenb; } _LIBUNWIND_ABORT("unsupported riscv register"); `````````` </details> https://github.com/llvm/llvm-project/pull/130286 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
