================
@@ -622,9 +644,14 @@ multiclass sme_quarter_outer_product_i16_i32<bit unsigned,
bit subtr, string mne
ZZ_h_mul_r_Lo,
ZZ_h_mul_r_Hi, mnemonic>;
}
-multiclass sme_quarter_outer_product_i64<bit zn_u, bit zm_u, bit subtr, string
mnemonic>{
+multiclass sme_quarter_outer_product_i64<bit zn_u, bit zm_u, bit subtr, string
mnemonic, string op>{
def _MZZ_HtoD : sme_quarter_outer_product_i64<{zn_u, 0}, {zm_u, 0}, subtr,
- ZPR16Mul2_Lo,
ZPR16Mul2_Hi, mnemonic>;
+ ZPR16Mul2_Lo,
ZPR16Mul2_Hi, mnemonic>, SMEPseudo2Instr<NAME # _MZZ_HtoD, 1>;
+
+ def NAME # _MZZ_HtoD # _PSEUDO :
sme2_quarter_tile_outer_product_pseudo_single_single<ZPR16Mul2_Lo,
ZPR16Mul2_Hi, SMEMatrixTileD>, SMEPseudo2Instr<NAME # _MZZ_HtoD, 0>;
+
+ def : SME2_ZA_Tile_TwoVec_Pat<NAME # _MZZ_HtoD, !cast<SDPatternOperator>(op
# "_1x1"), timm32_0_3, nxv8i16>;
----------------
CarolineConcatto wrote:
timm32_0_3 replace by timm32_0_7
"64-bit, single vectors" variants: is the name of the ZA tile ZA0-ZA7, encoded
in the "ZAda" field.
From:
https://developer.arm.com/documentation/ddi0602/2024-12/SME-Instructions/SMOP4A--4-way---Signed-integer-quarter-tile-sums-of-four-outer-products--accumulating-?lang=en
There is a correlations between SMEMatrixTypeEnum za_flag and "Operand
imm_ty:, they should both be of the same range.
https://github.com/llvm/llvm-project/pull/127797
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
