================ @@ -0,0 +1,1064 @@ +//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Base P' +// Packed SIMD instruction set extension. +// +// This version is still experimental as the 'P' extension hasn't been +// ratified yet. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +def simm10 : RISCVSImmLeafOp<10> { + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isInt<10>(Imm); + }]; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVPUnary<bits<5> funct5, bits<7> wuimm, + bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInstIBase<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1), + opcodestr, "$rd, $rs1"> { + let Inst{31-27} = funct5; + let Inst{26-20} = wuimm; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVPUnaryImm9<bits<7> funct7, string opcodestr, DAGOperand TyRd = GPR> + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs TyRd:$rd), (ins simm10:$simm10), + opcodestr, "$rd, $simm10"> { + bits<10> simm10; + + let Inst{31-25} = funct7; + let Inst{24-15} = simm10; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVPUnaryImm8<bits<8> funct8, string opcodestr, DAGOperand TyRd = GPR> + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs TyRd:$rd), (ins uimm8:$uimm8), + opcodestr, "$rd, $uimm8"> { + bits<8> uimm8; + let Inst{31-24} = funct8; + let Inst{23-16} = uimm8; + let Inst{15} = 0b0; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr> + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1), + opcodestr, "$rd, $rs1"> { + let Inst{31-27} = 0b11100; + let Inst{26-25} = w; + let Inst{24-20} = uf; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVPUnaryWUFRs1pRdp<bits<2> w, bits<5> uf, string opcodestr> + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPRPairRV32:$rdp), + (ins GPRPairRV32:$rs1p), opcodestr, "$rdp, $rs1p"> { + bits<4> rs1p; + bits<4> rdp; ---------------- topperc wrote:
How does GPRPairRV32 become a 4 bit value? GPRPairRV32 is an existing class used by Zacas which uses 5 bit registers. https://github.com/llvm/llvm-project/pull/123271 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
