================ @@ -0,0 +1,1064 @@ +//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Base P' +// Packed SIMD instruction set extension. +// +// This version is still experimental as the 'P' extension hasn't been +// ratified yet. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +def simm10 : RISCVSImmLeafOp<10> { + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isInt<10>(Imm); + }]; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVPUnary<bits<5> funct5, bits<7> wuimm, + bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInstIBase<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1), + opcodestr, "$rd, $rs1"> { + let Inst{31-27} = funct5; + let Inst{26-20} = wuimm; ---------------- topperc wrote:
Inconsistent identation. https://github.com/llvm/llvm-project/pull/123271 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
