[clang] [compiler-rt] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Ulrich Weigand via cfe-commits]

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@@ -102,6 +102,7 @@ SystemZTargetLowering::SystemZTargetLowering(const 
TargetMachine &TM,
     addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
   addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
   if (!useSoftFloat()) {
+    addRegisterClass(MVT::f16, &SystemZ::FP16BitRegClass);
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uweigand wrote:

Do we want to add a VR16BitRegClass if we have vector support?

https://github.com/llvm/llvm-project/pull/109164
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