================
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX :
RISCVProcessorModel<"syntacore-scr1-max",
FeatureStdExtC],
[TuneNoDefaultUnroll]>;
+def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
+ SyntacoreSCR3RV32Model,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtC],
+ [TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+
+def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
----------------
michaelmaitland wrote:
The PR title is misleading since it does not make clear that it adds a
processor. Can you please change that?
This PR is missing `clang/test/Driver/riscv-cpus.c` that are required to add
new processors. Can you also add to release notes that this processor is added?
https://github.com/llvm/llvm-project/pull/95427
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