================ @@ -0,0 +1,266 @@ +//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// + +// This model covers SYNTACORE_SCR3_RV32IMC and SYNTACORE_RV64IMAC +// configurations (syntacore-scr3-rv32/64). +// Overview: https://syntacore.com/products/scr3 + +// SCR3 is single-issue in-order processor +class SyntacoreSCR3Model : SchedMachineModel { + let MicroOpBufferSize = 0; + let IssueWidth = 1; + let LoadLatency = 2; + let MispredictPenalty = 3; + let CompleteModel = 0; + let UnsupportedFeatures = [HasStdExtD, HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, + HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, + HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, + HasVInstructions]; +} + +// Branching +multiclass SCR3_Branching<ProcResourceKind BRU> { + def : WriteRes<WriteJmp, [BRU]>; + def : WriteRes<WriteJal, [BRU]>; + def : WriteRes<WriteJalr, [BRU]>; +} + +// Single-cycle integer arithmetic and logic +multiclass SCR3_IntALU<ProcResourceKind ALU> { + def : WriteRes<WriteIALU, [ALU]>; + def : WriteRes<WriteIALU32, [ALU]>; + def : WriteRes<WriteShiftImm, [ALU]>; + def : WriteRes<WriteShiftImm32, [ALU]>; + def : WriteRes<WriteShiftReg, [ALU]>; + def : WriteRes<WriteShiftReg32, [ALU]>; +} + +// Integer multiplication +multiclass SCR3_IntMul<ProcResourceKind MUL> { + let Latency = 2 in { + def : WriteRes<WriteIMul, [MUL]>; + def : WriteRes<WriteIMul32, [MUL]>; + } +} + +// Integer division +multiclass SCR3_IntDiv<ProcResourceKind DIV, int DivLatency> { + let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in { + def : WriteRes<WriteIDiv, [DIV]>; + def : WriteRes<WriteIDiv32, [DIV]>; + def : WriteRes<WriteIRem, [DIV]>; + def : WriteRes<WriteIRem32, [DIV]>; + } +} + +// Load/store instructions on SCR3 have latency 2 +multiclass SCR3_Memory<ProcResourceKind LSU> { + let Latency = 2 in { + def : WriteRes<WriteSTB, [LSU]>; + def : WriteRes<WriteSTH, [LSU]>; + def : WriteRes<WriteSTW, [LSU]>; + def : WriteRes<WriteSTD, [LSU]>; + def : WriteRes<WriteLDB, [LSU]>; + def : WriteRes<WriteLDH, [LSU]>; + def : WriteRes<WriteLDW, [LSU]>; + def : WriteRes<WriteLDD, [LSU]>; + } +} + +// Atomic memory +multiclass SCR3_AtomicMemory<ProcResourceKind LSU> { + let Latency = 20 in { + def : WriteRes<WriteAtomicLDW, [LSU]>; + def : WriteRes<WriteAtomicLDD, [LSU]>; + def : WriteRes<WriteAtomicW, [LSU]>; + def : WriteRes<WriteAtomicD, [LSU]>; + def : WriteRes<WriteAtomicSTW, [LSU]>; + def : WriteRes<WriteAtomicSTD, [LSU]>; + } +} + +// Others +multiclass SCR3_Other { + def : WriteRes<WriteCSR, []>; + def : WriteRes<WriteNop, []>; + + def : InstRW<[WriteIALU], (instrs COPY)>; +} + + +multiclass SCR3_Unsupported { + defm : UnsupportedSchedSFB; + defm : UnsupportedSchedV; + defm : UnsupportedSchedXsfvcp; + defm : UnsupportedSchedZabha; + defm : UnsupportedSchedZba; + defm : UnsupportedSchedZbb; + defm : UnsupportedSchedZbc; + defm : UnsupportedSchedZbs; + defm : UnsupportedSchedZbkb; + defm : UnsupportedSchedZbkx; + defm : UnsupportedSchedZfa; + defm : UnsupportedSchedZfh; + defm : UnsupportedSchedZvk; + + let Unsupported = true in { ---------------- michaelmaitland wrote:
Should we have an `UnsupportedSchedF` and use it here? https://github.com/llvm/llvm-project/pull/95427 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
