https://github.com/asb updated https://github.com/llvm/llvm-project/pull/68113
>From 54783e0af749e95be28c47604e411236cca0efcc Mon Sep 17 00:00:00 2001
From: Alex Bradbury <a...@igalia.com>
Date: Tue, 3 Oct 2023 15:46:28 +0100
Subject: [PATCH 1/2] [RISCV] Mark the Zfa extension as non-experimental
Following the version bump in #67964 and the bug fix in #68026 I believe
we're ready to mark Zfa as non-experimental. For what it's worth, the
GCC torture suite passes now (though it's more of a litmus test than
anything else).
---
clang/test/Driver/riscv-arch.c | 18 +++++++++---------
.../test/Preprocessor/riscv-target-features.c | 8 ++++----
llvm/docs/RISCVUsage.rst | 4 +---
llvm/docs/ReleaseNotes.rst | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++--
llvm/test/CodeGen/RISCV/double-zfa.ll | 4 ++--
llvm/test/CodeGen/RISCV/fli-licm.ll | 4 ++--
llvm/test/CodeGen/RISCV/float-zfa.ll | 4 ++--
llvm/test/CodeGen/RISCV/half-zfa-fli.ll | 8 ++++----
llvm/test/CodeGen/RISCV/half-zfa.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll | 4 ++--
llvm/test/MC/RISCV/rv32zfa-only-valid.s | 6 +++---
llvm/test/MC/RISCV/zfa-double-invalid.s | 4 ++--
llvm/test/MC/RISCV/zfa-half-invalid.s | 4 ++--
llvm/test/MC/RISCV/zfa-invalid.s | 4 ++--
llvm/test/MC/RISCV/zfa-valid.s | 12 ++++++------
llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s | 12 ++++++------
llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 +-
20 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 4896c0184507dd4..0ac81ea982f1b61 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -372,24 +372,24 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG
%s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izfa'
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa
-menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS
%s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izfa'
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version
number
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa0p1
-menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS
%s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izfa0p1'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental
extension 'zfa' (this compiler supports 1.0)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental
extension 'ztso' (this compiler supports 0.1)
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa1p0
-menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zfa"
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 4b9ec423200017f..242197e3f129a3f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1001,11 +1001,11 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
-// RUN: %clang --target=riscv32-unknown-linux-gnu
-menable-experimental-extensions \
-// RUN: -march=rv32izfa1p0 -x c -E -dM %s \
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32izfa -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
-// RUN: %clang --target=riscv64-unknown-linux-gnu
-menable-experimental-extensions \
-// RUN: -march=rv64izfa1p0 -x c -E -dM %s \
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izfa -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 23edaa6f29941de..6812efaeb36e0c1 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -109,6 +109,7 @@ on support follow.
``Zcmp`` Assembly Support
``Zcmt`` Assembly Support
``Zdinx`` Supported
+ ``Zfa`` Supported
``Zfh`` Supported
``Zfhmin`` Supported
``Zfinx`` Supported
@@ -196,9 +197,6 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification
<https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
-``experimental-zfa``
- LLVM implements the `1.0 specification
<https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-056b6ff-2023-10-02>`__.
-
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
<https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index f68a1cae73412e7..f0d4b5c5dfc7aff 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -109,7 +109,7 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------
-* The Zfa extension version was upgraded to 1.0.
+* The Zfa extension version was upgraded to 1.0 and is no longer experimental.
* Zihintntl extension version was upgraded to 1.0 and is no longer
experimental.
Changes to the WebAssembly Backend
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 9c7670d35a7c899..72d33e1e65c8f58 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -106,6 +106,7 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zdinx", RISCVExtensionVersion{1, 0}},
+ {"zfa", RISCVExtensionVersion{1, 0}},
{"zfh", RISCVExtensionVersion{1, 0}},
{"zfhmin", RISCVExtensionVersion{1, 0}},
{"zfinx", RISCVExtensionVersion{1, 0}},
@@ -166,7 +167,6 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zacas", RISCVExtensionVersion{1, 0}},
- {"zfa", RISCVExtensionVersion{1, 0}},
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3f099198f2a5f91..3d3486b7fa89563 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -159,7 +159,7 @@ def HasStdExtZhinxOrZhinxmin
"'Zhinxmin' (Half Float in Integer
Minimal)">;
def FeatureStdExtZfa
- : SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
+ : SubtargetFeature<"zfa", "HasStdExtZfa", "true",
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 5c8812cd55a5064..c28594088dac5cd 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -63,7 +63,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZIFENCEI %s
; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZICNTR %s
; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZIHPM %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfa %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - |
FileCheck --check-prefix=RV32ZVBB %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - |
FileCheck --check-prefix=RV32ZVBC %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - |
FileCheck --check-prefix=RV32ZVKB %s
@@ -153,7 +153,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZIFENCEI %s
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZICNTR %s
; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZIHPM %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfa %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - |
FileCheck --check-prefix=RV64ZVBB %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - |
FileCheck --check-prefix=RV64ZVBC %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - |
FileCheck --check-prefix=RV64ZVKB %s
diff --git a/llvm/test/CodeGen/RISCV/double-zfa.ll
b/llvm/test/CodeGen/RISCV/double-zfa.ll
index d81b7ddafd81851..904dd9f2ccbef91 100644
--- a/llvm/test/CodeGen/RISCV/double-zfa.ll
+++ b/llvm/test/CodeGen/RISCV/double-zfa.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfa,+d <
%s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfa,+d < %s \
; RUN: | FileCheck --check-prefixes=CHECK,RV32IDZFA %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfa,+d < %s
\
+; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfa,+d < %s \
; RUN: | FileCheck --check-prefixes=CHECK,RV64DZFA %s
define double @loadfpimm1() {
diff --git a/llvm/test/CodeGen/RISCV/fli-licm.ll
b/llvm/test/CodeGen/RISCV/fli-licm.ll
index f37ace801b1595e..4962a146362d56a 100644
--- a/llvm/test/CodeGen/RISCV/fli-licm.ll
+++ b/llvm/test/CodeGen/RISCV/fli-licm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+experimental-zfa \
+; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+zfa \
; RUN: | FileCheck %s --check-prefix=RV32
-; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+experimental-zfa \
+; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+zfa \
; RUN: | FileCheck %s --check-prefix=RV64
; The purpose of this test is to check that an FLI instruction that
diff --git a/llvm/test/CodeGen/RISCV/float-zfa.ll
b/llvm/test/CodeGen/RISCV/float-zfa.ll
index 3b9043b0afe24b6..baa45e00b565fb5 100644
--- a/llvm/test/CodeGen/RISCV/float-zfa.ll
+++ b/llvm/test/CodeGen/RISCV/float-zfa.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa < %s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa < %s \
; RUN: | FileCheck %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa < %s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa < %s \
; RUN: | FileCheck %s
define float @loadfpimm1() {
diff --git a/llvm/test/CodeGen/RISCV/half-zfa-fli.ll
b/llvm/test/CodeGen/RISCV/half-zfa-fli.ll
index cab15e58b0bb823..2805a8e582b34b9 100644
--- a/llvm/test/CodeGen/RISCV/half-zfa-fli.ll
+++ b/llvm/test/CodeGen/RISCV/half-zfa-fli.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh <
%s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh <
%s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f
-mattr=+experimental-zfa,+zfhmin < %s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfhmin < %s \
; RUN: | FileCheck %s --check-prefix=ZFHMIN
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfhmin
< %s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfhmin < %s \
; RUN: | FileCheck %s --check-prefix=ZFHMIN
define half @loadfpimm1() {
diff --git a/llvm/test/CodeGen/RISCV/half-zfa.ll
b/llvm/test/CodeGen/RISCV/half-zfa.ll
index 732075e186b29f1..93ffcb8a1a05c2b 100644
--- a/llvm/test/CodeGen/RISCV/half-zfa.ll
+++ b/llvm/test/CodeGen/RISCV/half-zfa.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh <
%s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh <
%s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
declare half @llvm.minimum.f16(half, half)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
b/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
index 7225677e61f606f..59be018efb857b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi
ilp32d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zfh,+zfa,+zvfh,+v -target-abi ilp32d
-verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi
lp64d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zfh,+zfa,+zvfh,+v -target-abi lp64d
-verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK
define <vscale x 8 x half> @vsplat_f16_0p625() {
diff --git a/llvm/test/MC/RISCV/rv32zfa-only-valid.s
b/llvm/test/MC/RISCV/rv32zfa-only-valid.s
index 2cf5c1c42f3e7a2..d212659d5208d79 100644
--- a/llvm/test/MC/RISCV/rv32zfa-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32zfa-only-valid.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh
-riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases
-show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh
< %s \
-# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d
-r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \
diff --git a/llvm/test/MC/RISCV/zfa-double-invalid.s
b/llvm/test/MC/RISCV/zfa-double-invalid.s
index 3a92b18d6b19d0f..ec21b0c613375af 100644
--- a/llvm/test/MC/RISCV/zfa-double-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-double-invalid.s
@@ -1,7 +1,7 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+zfh \
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+zfh \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+zfh \
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+zfh \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
diff --git a/llvm/test/MC/RISCV/zfa-half-invalid.s
b/llvm/test/MC/RISCV/zfa-half-invalid.s
index f916c9bd66daa59..a2c6f09043084fe 100644
--- a/llvm/test/MC/RISCV/zfa-half-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-half-invalid.s
@@ -1,7 +1,7 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d \
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d \
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index e48618506626be3..c2537c3fc510246 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1
| FileCheck -check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1
| FileCheck -check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck
-check-prefixes=CHECK-NO-RV64 %s
# Invalid rounding modes
# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
diff --git a/llvm/test/MC/RISCV/zfa-valid.s b/llvm/test/MC/RISCV/zfa-valid.s
index 5207746570558c2..e951c9da2ba788c 100644
--- a/llvm/test/MC/RISCV/zfa-valid.s
+++ b/llvm/test/MC/RISCV/zfa-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh
-riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases
-show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh
-riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+d,+zfh -riscv-no-aliases
-show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh
< %s \
-# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d
-r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh
< %s \
-# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d
-r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+d,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \
diff --git a/llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
b/llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
index 6506404d966bf20..6b5dc9200f34ccb 100644
--- a/llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
+++ b/llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+zvfh
-riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+zfhmin,+zvfh -riscv-no-aliases
-show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+zvfh
-riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+zfhmin,+zvfh -riscv-no-aliases
-show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32
-mattr=+experimental-zfa,+zfhmin,+zvfh < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+zvfh -M
no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+zfhmin,+zvfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64
-mattr=+experimental-zfa,+zfhmin,+zvfh < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+zvfh -M
no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+zfhmin,+zvfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp
b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 4eeaab727c5c01b..90e26a23e87c205 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -653,6 +653,7 @@ R"(All available -march extensions for RISC-V
zihpm 2.0
zmmul 1.0
zawrs 1.0
+ zfa 1.0
zfh 1.0
zfhmin 1.0
zfinx 1.0
@@ -729,7 +730,6 @@ Experimental extensions
zicfilp 0.2 This is a long dummy description
zicond 1.0
zacas 1.0
- zfa 1.0
zfbfmin 0.8
ztso 0.1
zvbb 1.0
>From 234c3a9353b41c8e6a3e8c6146b0993bf6efbcf6 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <a...@igalia.com>
Date: Tue, 3 Oct 2023 17:46:30 +0100
Subject: [PATCH 2/2] Remove note about Zfa being experimental from
RISCVInstrInfoZfa.td
---
llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 07d07d765e61e66..5d6e8821b85931a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -8,7 +8,6 @@
//
// This file describes the RISC-V instructions from the standard 'Zfa'
// additional floating-point extension, version 1.0.
-// This version is still experimental.
//
//===----------------------------------------------------------------------===//
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