llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-driver <details> <summary>Changes</summary> Following the version bump in #<!-- -->67964 and the bug fix in #<!-- -->68026 I believe we're ready to mark Zfa as non-experimental. I'll note the GCC torture suite passes now with Zfa enabled (though it's more of a litmus test than anything else). This PR is stacked on top of #<!-- -->67694 - only the most recent commit should be reviewed. --- Patch is 22.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/68113.diff 21 Files Affected: - (modified) clang/test/Driver/riscv-arch.c (+9-9) - (modified) clang/test/Preprocessor/riscv-target-features.c (+5-5) - (modified) llvm/docs/RISCVUsage.rst (+1-3) - (modified) llvm/docs/ReleaseNotes.rst (+1) - (modified) llvm/lib/Support/RISCVISAInfo.cpp (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4-4) - (modified) llvm/test/CodeGen/RISCV/double-zfa.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/fli-licm.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/float-zfa.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/half-zfa-fli.ll (+4-4) - (modified) llvm/test/CodeGen/RISCV/half-zfa.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll (+2-2) - (modified) llvm/test/MC/RISCV/attribute-arch.s (+2-2) - (modified) llvm/test/MC/RISCV/rv32zfa-only-valid.s (+3-3) - (modified) llvm/test/MC/RISCV/zfa-double-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/zfa-half-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/zfa-invalid.s (+2-2) - (modified) llvm/test/MC/RISCV/zfa-valid.s (+6-6) - (modified) llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s (+6-6) - (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1-1) ``````````diff diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 92a6a59cba2317c..0ac81ea982f1b61 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -372,24 +372,24 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s // RV32-ZFHMIN: "-target-feature" "+zfhmin" -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s -// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izfa' +// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso' // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s -// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izfa' +// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso' // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa0p1 -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s -// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izfa0p1' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zfa' (this compiler supports 0.2) +// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7' +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'ztso' (this compiler supports 0.1) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa0p2 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s -// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zfa" +// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso" // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 4dd83cfa0620b90..242197e3f129a3f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1001,13 +1001,13 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s // CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}} -// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izfa0p2 -x c -E -dM %s \ +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32izfa -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s -// RUN: %clang --target=riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izfa0p2 -x c -E -dM %s \ +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64izfa -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s -// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}} +// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izfbfmin0p8 -x c -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 8d12d58738c609a..6812efaeb36e0c1 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -109,6 +109,7 @@ on support follow. ``Zcmp`` Assembly Support ``Zcmt`` Assembly Support ``Zdinx`` Supported + ``Zfa`` Supported ``Zfh`` Supported ``Zfhmin`` Supported ``Zfinx`` Supported @@ -196,9 +197,6 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zacas`` LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_. -``experimental-zfa`` - LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/zfa-20230414.pdf>`__. - ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 660bb4e70a5a707..f0d4b5c5dfc7aff 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -109,6 +109,7 @@ Changes to the PowerPC Backend Changes to the RISC-V Backend ----------------------------- +* The Zfa extension version was upgraded to 1.0 and is no longer experimental. * Zihintntl extension version was upgraded to 1.0 and is no longer experimental. Changes to the WebAssembly Backend diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index c4f50b7773b75df..72d33e1e65c8f58 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -106,6 +106,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zdinx", RISCVExtensionVersion{1, 0}}, + {"zfa", RISCVExtensionVersion{1, 0}}, {"zfh", RISCVExtensionVersion{1, 0}}, {"zfhmin", RISCVExtensionVersion{1, 0}}, {"zfinx", RISCVExtensionVersion{1, 0}}, @@ -166,7 +167,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zacas", RISCVExtensionVersion{1, 0}}, - {"zfa", RISCVExtensionVersion{0, 2}}, {"zfbfmin", RISCVExtensionVersion{0, 8}}, {"zicfilp", RISCVExtensionVersion{0, 2}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3f099198f2a5f91..3d3486b7fa89563 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -159,7 +159,7 @@ def HasStdExtZhinxOrZhinxmin "'Zhinxmin' (Half Float in Integer Minimal)">; def FeatureStdExtZfa - : SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true", + : SubtargetFeature<"zfa", "HasStdExtZfa", "true", "'Zfa' (Additional Floating-Point)", [FeatureStdExtF]>; def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 29eaaee57868a83..c28594088dac5cd 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -63,7 +63,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s ; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s ; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHPM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s +; RUN: llc -mtriple=riscv32 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s @@ -153,7 +153,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s ; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s ; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHPM %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s +; RUN: llc -mtriple=riscv64 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s @@ -243,7 +243,7 @@ ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr2p0_zicsr2p0" ; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm2p0" -; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" +; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa1p0" ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0" ; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0" @@ -332,7 +332,7 @@ ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0" ; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr2p0_zicsr2p0" ; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm2p0" -; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2" +; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa1p0" ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0" ; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0" diff --git a/llvm/test/CodeGen/RISCV/double-zfa.ll b/llvm/test/CodeGen/RISCV/double-zfa.ll index 881430f6f5ffdd2..184a73b129ed23a 100644 --- a/llvm/test/CodeGen/RISCV/double-zfa.ll +++ b/llvm/test/CodeGen/RISCV/double-zfa.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfa,+d < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfa,+d < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,RV32IDZFA %s -; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfa,+d < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfa,+d < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,RV64DZFA %s define double @loadfpimm1() { diff --git a/llvm/test/CodeGen/RISCV/fli-licm.ll b/llvm/test/CodeGen/RISCV/fli-licm.ll index f37ace801b1595e..4962a146362d56a 100644 --- a/llvm/test/CodeGen/RISCV/fli-licm.ll +++ b/llvm/test/CodeGen/RISCV/fli-licm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+experimental-zfa \ +; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+zfa \ ; RUN: | FileCheck %s --check-prefix=RV32 -; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+experimental-zfa \ +; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+zfa \ ; RUN: | FileCheck %s --check-prefix=RV64 ; The purpose of this test is to check that an FLI instruction that diff --git a/llvm/test/CodeGen/RISCV/float-zfa.ll b/llvm/test/CodeGen/RISCV/float-zfa.ll index 94da29bd6bece8a..df92f3fce5aa471 100644 --- a/llvm/test/CodeGen/RISCV/float-zfa.ll +++ b/llvm/test/CodeGen/RISCV/float-zfa.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa < %s \ ; RUN: | FileCheck %s -; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa < %s \ ; RUN: | FileCheck %s define float @loadfpimm1() { diff --git a/llvm/test/CodeGen/RISCV/half-zfa-fli.ll b/llvm/test/CodeGen/RISCV/half-zfa-fli.ll index f82ae5c00d15962..4fc6d50476b24f9 100644 --- a/llvm/test/CodeGen/RISCV/half-zfa-fli.ll +++ b/llvm/test/CodeGen/RISCV/half-zfa-fli.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \ ; RUN: | FileCheck %s -; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \ ; RUN: | FileCheck %s -; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfhmin < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfhmin < %s \ ; RUN: | FileCheck %s --check-prefix=ZFHMIN -; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfhmin < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfhmin < %s \ ; RUN: | FileCheck %s --check-prefix=ZFHMIN define half @loadfpimm1() { diff --git a/llvm/test/CodeGen/RISCV/half-zfa.ll b/llvm/test/CodeGen/RISCV/half-zfa.ll index 732075e186b29f1..93ffcb8a1a05c2b 100644 --- a/llvm/test/CodeGen/RISCV/half-zfa.ll +++ b/llvm/test/CodeGen/RISCV/half-zfa.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \ ; RUN: | FileCheck %s -; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \ +; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \ ; RUN: | FileCheck %s declare half @llvm.minimum.f16(half, half) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll index 7225677e61f606f..59be018efb857b5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zfh,+zfa,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK -; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zfh,+zfa,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK define <vscale x 8 x half> @vsplat_f16_0p625() { diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index bf40eda456edf13..12c494dc896a0ad 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -261,8 +261,8 @@ .attribute arch, "rv32izifencei2p0" # CHECK: attribute 5, "rv32i2p1_zifencei2p0" -.attribute arch, "rv32izfa0p2" -# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" +.attribute arch, "rv32izfa1p0" +# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa1p0" .attribute arch, "rv32izicond1p0" # CHECK: attribute 5, "rv32i2p1_zicond1p0" diff --git a/llvm/test/MC/RISCV/rv32zfa-only-valid.s b/llvm/test/MC/RISCV/rv32zfa-only-valid.s index 2cf5c1c42f3e7a2..d212659d5208d79 100644 --- a/llvm/test/MC/RISCV/rv32zfa-only-valid.s +++ b/llvm/test/MC/RISCV/rv32zfa-only-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \ +# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \ diff --git a/llvm/test/MC/RISCV/zfa-double-invalid.s b/llvm/test/MC/RISCV/zfa-double-invalid.s index 3a92b18d6b19d0f..ec21b0c613375af 100644 --- a/llvm/test/MC/RISCV/zfa-double-invalid.s +++ b/llvm/test/MC/RISCV/zfa-double-invalid.s @@ -1,7 +1,7 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+zfh \ +# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+zfh \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+zfh \ +# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+zfh \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s diff --git a/llvm/test/MC/RISCV/zfa-half-invalid.s b/llvm/test/MC/RISCV/zfa-half-invalid.s index f916c9bd66daa59..a2c6f09043084fe 100644 --- a/llvm/test/MC/RISCV/zfa-half-invalid.s +++ b/llvm/test/MC/RISCV/zfa-half-invalid.s @@ -1,7 +1,7 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d \ +# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d \ +# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s index e48618506626be3..c2537c3fc510246 100644 --- a/llvm/test/MC/RISCV/zfa-invalid.s +++ b/llvm/test/MC/RISCV/zfa-invalid.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s +# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s +# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s # Invalid rounding modes # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode diff --git a/llvm/test/MC/RISCV/zfa-valid.s b/llvm/test/MC/RISCV/zfa-valid.s index 5207746570558c2..e951c9da2ba788c 100644 --- a/llvm/test/MC/RISCV/zfa-valid.s +++ b/llvm/test/MC/RISCV/zfa-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \ +# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+d,+zfh < %s \ +# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \ diff --git a/llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s b/llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s index 6506404d966bf20..6b5dc9200f34ccb 100644 --- a/llvm/test/MC/RISCV/zfa-zfhmin-zv... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/68113 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
