shenhan marked 3 inline comments as done.
shenhan added inline comments.
================
Comment at: llvm/lib/CodeGen/TargetPassConfig.cpp:1278
}
- addPass(createMachineFunctionSplitterPass());
+ if (TM->getTargetTriple().isX86())
+ addPass(createMachineFunctionSplitterPass());
----------------
shenhan wrote:
> snehasish wrote:
> > Can you coordinate with @dhoekwater ? He has some patches in flight for
> > AArch64.
> >
> > I think D157157 is the one which modifies the same logic.
> Thanks. Yes, I'll coordinate with @dhoekwater before resolving this.
@dhoekwater will rebase D157157 on top of this.
================
Comment at: llvm/test/CodeGen/X86/mfs-triple.ll:8
+
+define void @foo4(i1 zeroext %0, i1 zeroext %1) nounwind {
+ br i1 %0, label %3, label %7
----------------
snehasish wrote:
> Any reason why we can't use the bitcode already in
> test/CodeGen/machine-function-splitter.ll? (Going to be moved to
> test/Generic/machine-function-splitter.ll in D157563)
>
> IMO we can just reuse the basic test and add these run and check lines.
Moved the tests into machine-function-splitter.ll. Either this CL or D157563
can be submitted first, and the other will rebase on top of that.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D157750/new/
https://reviews.llvm.org/D157750
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