Author: eopXD Date: 2023-05-22T04:20:09-07:00 New Revision: 827f43918836fa3a2ec1abaf3592fb4a74dcaf48
URL: https://github.com/llvm/llvm-project/commit/827f43918836fa3a2ec1abaf3592fb4a74dcaf48 DIFF: https://github.com/llvm/llvm-project/commit/827f43918836fa3a2ec1abaf3592fb4a74dcaf48.diff LOG: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32 For the cover letter of this patch-set, please checkout D146872. Depends on D147913. This is the 8th patch of the patch-set. This patch is a proof-of-concept and will be extended to full coverage in the future. Currently, the old non-tuple indexed segment load is not removed, and only signed integer indexed segment load of NF=2, EEW=32 is defined here. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D147914 Added: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c Modified: clang/include/clang/Basic/riscv_vector.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index ca0227cb6edb5..72d037512dcab 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1744,6 +1744,57 @@ multiclass RVVStridedSegStoreTuple<string op> { } } +multiclass RVVIndexedSegLoadTuple<string op> { + foreach type = ["i"] in { + foreach eew_info = [["32", "(Log2EEW:5)"]] in { + defvar eew = eew_info[0]; + defvar eew_type = eew_info[1]; + foreach nf = [2] in { + let Name = op # nf # "ei" # eew # "_v_tuple", + OverloadedName = op # nf # "ei" # eew # "_tuple", + IRName = op # nf, + MaskedIRName = op # nf # "_mask", + NF = nf, + ManualCodegen = [{ + { + assert(((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) || + (!IsMasked && (PolicyAttrs & RVV_VTA))) && + "FIXME: Only handling default policy (TAMA) for now"); + + llvm::Type *ElementVectorType = cast<StructType>(ResultType)->elements()[0]; + + SmallVector<llvm::Value*, 12> Operands; + + Operands.append(NF, llvm::PoisonValue::get(ElementVectorType)); + + unsigned Offset = IsMasked ? 1 : 0; + Operands.push_back(Ops[Offset]); // Ptr + Operands.push_back(Ops[Offset + 1]); // Idx + if (IsMasked) + Operands.push_back(Ops[0]); + Operands.push_back(Ops[Offset + 2]); // VL + if (IsMasked) + Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs)); + + IntrinsicTypes = {ElementVectorType, Ops[Offset + 1]->getType(), + Ops.back()->getType()}; + llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); + llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); + + if (ReturnValue.isNull()) + return LoadValue; + else + return Builder.CreateStore(LoadValue, ReturnValue.getValue()); + } + }] in { + defvar T = "(Tuple:" # nf # ")"; + def : RVVBuiltin<"v", T # "vPCe" # eew_type # "Uv", type>; + } + } + } + } +} + // TODO: Extend for policy let UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy, @@ -1751,6 +1802,8 @@ let UnMaskedPolicyScheme = NonePolicy, defm : RVVUnitStridedSegLoadTuple<"vlseg">; defm : RVVUnitStridedSegLoadFFTuple<"vlseg">; defm : RVVStridedSegLoadTuple<"vlsseg">; +defm : RVVIndexedSegLoadTuple<"vluxseg">; +defm : RVVIndexedSegLoadTuple<"vloxseg">; } let UnMaskedPolicyScheme = NonePolicy, diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c new file mode 100644 index 0000000000000..e626b19b147d6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <riscv_vector.h> + +// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vloxseg2ei32_v_tuple_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i32> [[BINDEX]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]] +// +vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) { + return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl); +} + +// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vloxseg2ei32_v_tuple_i32m1_m +// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i32> [[BINDEX]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]] +// +vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) { + return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c new file mode 100644 index 0000000000000..412e45e1fc81a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <riscv_vector.h> + +// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vluxseg2ei32_v_tuple_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i32> [[BINDEX]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]] +// +vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) { + return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl); +} + +// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vluxseg2ei32_v_tuple_i32m1_m +// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i32> [[BINDEX]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]] +// +vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) { + return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl); +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
