Author: eopXD Date: 2023-05-22T04:13:51-07:00 New Revision: f2ffdaaae6bf246a8bc00b4b9924393d10835264
URL: https://github.com/llvm/llvm-project/commit/f2ffdaaae6bf246a8bc00b4b9924393d10835264 DIFF: https://github.com/llvm/llvm-project/commit/f2ffdaaae6bf246a8bc00b4b9924393d10835264.diff LOG: [7/11][POC][Clang][RISCV] Define tuple type variant of vssseg2e32 For the cover letter of this patch-set, please checkout D146872. Depends on D147912. This is the 7th patch of the patch-set. This patch is a proof-of-concept and will be extended to full coverage in the future. Currently, the old non-tuple strided segment store is not removed, and only signed integer strided segment store of NF=2, EEW=32 is defined here. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D147913 Added: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32_tuple.c Modified: clang/include/clang/Basic/riscv_vector.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index b323ac57bdeb4..ca0227cb6edb5 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1699,6 +1699,51 @@ multiclass RVVStridedSegLoadTuple<string op> { } } +multiclass RVVStridedSegStoreTuple<string op> { + foreach type = ["i"] in { + defvar eew = !cond(!eq(type, "i") : "32"); + foreach nf = [2] in { + let Name = op # nf # "e" # eew # "_v_tuple", + OverloadedName = op # nf # "e" # eew # "_tuple", + IRName = op # nf, + MaskedIRName = op # nf # "_mask", + NF = nf, + HasMaskedOffOperand = false, + MaskedPolicyScheme = NonePolicy, + ManualCodegen = [{ + { + // Masked + // Builtin: (mask, ptr, stride, v_tuple, vl) + // Intrinsic: (val0, val1, ..., ptr, stride, mask, vl) + // Unmasked + // Builtin: (ptr, stride, v_tuple, vl) + // Intrinsic: (val0, val1, ..., ptr, stride, vl) + unsigned Offset = IsMasked ? 1 : 0; + llvm::Value *VTupleOperand = Ops[Offset + 2]; + + SmallVector<llvm::Value*, 12> Operands; + for (unsigned I = 0; I < NF; ++I) { + llvm::Value *V = Builder.CreateExtractValue(VTupleOperand, {I}); + Operands.push_back(V); + } + Operands.push_back(Ops[Offset]); // Ptr + Operands.push_back(Ops[Offset + 1]); // Stride + if (IsMasked) + Operands.push_back(Ops[0]); + Operands.push_back(Ops[Offset + 3]); // VL + + IntrinsicTypes = {Operands[0]->getType(), Operands.back()->getType()}; + llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); + return Builder.CreateCall(F, Operands, ""); + } + }] in { + defvar T = "(Tuple:" # nf # ")"; + def : RVVBuiltin<"v", "0Pet" # T # "v", type>; + } + } + } +} + // TODO: Extend for policy let UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy, @@ -1712,6 +1757,7 @@ let UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy, IsTuple = true in { defm : RVVUnitStridedSegStoreTuple<"vsseg">; +defm : RVVStridedSegStoreTuple<"vssseg">; } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32_tuple.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32_tuple.c new file mode 100644 index 0000000000000..548e1104b9b7d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32_tuple.c @@ -0,0 +1,36 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <riscv_vector.h> + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e32_v_tuple_i32m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE0:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv2i32.i64(<vscale x 2 x i32> [[TMP2]], <vscale x 2 x i32> [[TMP3]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e32_v_tuple_i32m1(int32_t *base, ptr diff _t bstride, vint32m1x2_t v_tuple, size_t vl) { + return __riscv_vssseg2e32_v_tuple_i32m1(base, bstride, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e32_v_tuple_i32m1_m +// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE0:%.*]], <vscale x 2 x i32> [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP2]], <vscale x 2 x i32> [[TMP3]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, ptr diff _t bstride, vint32m1x2_t v_tuple, size_t vl) { + return __riscv_vssseg2e32_v_tuple_i32m1_m(mask, base, bstride, v_tuple, vl); +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
