VincentWu updated this revision to Diff 456224.
VincentWu marked 2 inline comments as done.
VincentWu added a comment.
set zcb inst Sched info same as their uncompressed forms
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131141/new/
https://reviews.llvm.org/D131141
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32zcb-invalid.s
llvm/test/MC/RISCV/rv32zcb-valid.s
llvm/test/MC/RISCV/rv64zcb-valid.s
Index: llvm/test/MC/RISCV/rv64zcb-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zcb-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN: | llvm-objdump --mattr=+m,+zbb,+zba,experimental-zcb -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-RV64 %s
+
+# CHECK-ASM-AND-OBJ: c.zext.w s0
+# CHECK-ASM: encoding: [0x71,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zba' (Address Generation Instructions), 'Zcb' (Shortened format for basic bit manipulation instructions)
+# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
+c.zext.w s0
Index: llvm/test/MC/RISCV/rv32zcb-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zcb-valid.s
@@ -0,0 +1,72 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+m,+zbb,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+m,+zbb,+experimental-zcb < %s \
+# RUN: | llvm-objdump --mattr=+m,+zbb,+experimental-zcb -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN: | llvm-objdump --mattr=+m,+zbb,+zba,experimental-zcb -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: c.zext.b s0
+# CHECK-ASM: encoding: [0x61,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions)
+c.zext.b s0
+
+# CHECK-ASM-AND-OBJ: c.sext.b s0
+# CHECK-ASM: encoding: [0x65,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.sext.b s0
+
+# CHECK-ASM-AND-OBJ: c.zext.h s0
+# CHECK-ASM: encoding: [0x69,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.zext.h s0
+
+# CHECK-ASM-AND-OBJ: c.sext.h s0
+# CHECK-ASM: encoding: [0x6d,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.sext.h s0
+
+# CHECK-ASM-AND-OBJ: c.not s0
+# CHECK-ASM: encoding: [0x75,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.not s0
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'M' (Integer Multiplication and Division) or 'Zmmul' (Integer Multiplication), 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.mul s0, s1
+
+# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x83]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.lbu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.lhu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.lh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x8b]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.sb a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x8f]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.sh a5, 2(a4)
Index: llvm/test/MC/RISCV/rv32zcb-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zcb-invalid.s
@@ -0,0 +1,19 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=experimental-zcb -riscv-no-aliases -show-encoding %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=experimental-zcb -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 3]
+c.lbu a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.lhu a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.lh a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 3]
+c.sb a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.sh a5, 10(a4)
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -190,3 +190,6 @@
.attribute arch, "rv32izca0p70"
# CHECK: attribute 5, "rv32i2p0_zca0p70"
+
+.attribute arch, "rv32izcb0p70"
+# CHECK: attribute 5, "rv32i2p0_zca0p70_zcb0p70"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -62,6 +62,7 @@
bool HasStdExtZbs = false;
bool HasStdExtZbt = false;
bool HasStdExtZca = false;
+ bool HasStdExtZcb = false;
bool HasStdExtV = false;
bool HasStdExtZve32x = false;
bool HasStdExtZve32f = false;
@@ -171,6 +172,7 @@
bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZbt() const { return HasStdExtZbt; }
bool hasStdExtZca() const { return HasStdExtZca; }
+ bool hasStdExtZcb() const { return HasStdExtZcb; }
bool hasStdExtZvl() const { return ZvlLen != 0; }
bool hasStdExtZvfh() const { return HasStdExtZvfh; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -0,0 +1,179 @@
+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the 'Zc' Code-size
+/// reduction extension, version 0.70.4.
+/// This version is still experimental as the 'Zc' extension hasn't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm2_zc : Operand<XLenVT>,
+ ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<2>;
+ let DecoderMethod = "decodeUImmOperand<2>";
+ let OperandType = "OPERAND_UIMM2";
+ let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isUInt<2>(Imm);
+ }];
+}
+
+def uimm2_lsb0 : Operand<XLenVT>,
+ ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<2, "Lsb0">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeUImmOperand<2>";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<1, 1>(Imm);
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVZcArith_r<bits<2> funct2, bits<3> opcode, string opcodestr>
+ : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs),
+ opcodestr, "$rs", [], InstFormatCB>{
+ bits<3> rs;
+ let Constraints = "$rs = $rs_wb";
+
+ let Inst{15-13} = 0b100;
+ let Inst{12-10} = 0b111;
+ let Inst{9-7} = rs;
+ let Inst{6-5} = funct2;
+ let Inst{4-2} = opcode;
+ let Inst{1-0} = 0b01;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVZcArith_rr<bits<6> funct6,bits<2> funct2, bits<2> opcode, string opcodestr>
+ : RVInst16<(outs GPRC:$rs1_wb), (ins GPRC:$rs1, GPRC:$rs2),
+ opcodestr, "$rs1, $rs2", [], InstFormatCB> {
+ bits<3> rs1;
+ bits<3> rs2;
+ let Constraints = "$rs1 = $rs1_wb";
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rs1;
+ let Inst{6-5} = funct2;
+ let Inst{4-2} = rs2;
+ let Inst{1-0} = opcode;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ZcLoad_ri<bits<3> funct3, bits<2> opcode, string opcodestr,
+ RegisterClass cls, DAGOperand opnd>
+ : RVInst16CL<funct3, opcode, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
+ opcodestr, "$rd, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class ZcStore_ri<bits<3> funct3, bits<2> opcode, string opcodestr,
+ RegisterClass cls, DAGOperand opnd>
+ : RVInst16CS<funct3, opcode, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
+ opcodestr, "$rs2, ${imm}(${rs1})">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// ZCB
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in {
+def C_ZEXT_W : RVZcArith_r<0b11, 0b100 , "c.zext.w">,
+ Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
+}
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in {
+def C_ZEXT_H : RVZcArith_r<0b11, 0b010 , "c.zext.h">,
+ Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_B : RVZcArith_r<0b11, 0b001 , "c.sext.b">,
+ Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_H : RVZcArith_r<0b11, 0b011 , "c.sext.h">,
+ Sched<[WriteIALU, ReadIALU]>;
+}
+
+let Predicates = [HasStdExtZcb] in
+def C_ZEXT_B : RVZcArith_r<0b11, 0b000 , "c.zext.b">,
+ Sched<[WriteIALU, ReadIALU]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
+def C_MUL : RVZcArith_rr<0b100111, 0b10, 0b01, "c.mul">,
+ Sched<[WriteIMul, ReadIMul, ReadIMul]>;
+
+let Predicates = [HasStdExtZcb] in {
+def C_NOT : RVZcArith_r<0b11, 0b101 , "c.not">,
+ Sched<[WriteIALU, ReadIALU]>;
+
+def C_LBU : ZcLoad_ri<0b100, 0b00, "c.lbu", GPRC, uimm2_zc>,
+ Sched<[WriteLDB, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b000;
+ let Inst{6-5} = imm{0,1};
+}
+
+def C_LHU : ZcLoad_ri<0b100, 0b00, "c.lhu", GPRC, uimm2_lsb0>,
+ Sched<[WriteLDH, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b001;
+ let Inst{6} = 0b0;
+ let Inst{5} = imm{1};
+}
+
+def C_LH : ZcLoad_ri<0b100, 0b00, "c.lh", GPRC, uimm2_lsb0>,
+ Sched<[WriteLDH, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b001;
+ let Inst{6} = 0b1;
+ let Inst{5} = imm{1};
+}
+
+def C_SB : ZcStore_ri<0b100, 0b00, "c.sb", GPRC, uimm2_zc>,
+ Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b010;
+ let Inst{6-5} = imm{0,1};
+}
+
+def C_SH : ZcStore_ri<0b100, 0b00, "c.sh", GPRC, uimm2_lsb0>,
+ Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b011;
+ let Inst{6} = 0b1;
+ let Inst{5} = imm{1};
+}
+}
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb] in {
+ def : InstAlias<"c.lbu $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+ def : InstAlias<"c.lhu $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+ def : InstAlias<"c.lh $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+ def : InstAlias<"c.sb $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+ def : InstAlias<"c.sh $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1688,6 +1688,7 @@
include "RISCVInstrInfoD.td"
include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZb.td"
+include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -360,6 +360,14 @@
"'C' (Compressed Instructions) or "
"'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+def FeatureExtZcb
+ : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
+ "'Zcb' (Shortened format for basic bit manipulation instructions)",
+ [FeatureExtZca]>;
+def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
+ AssemblerPredicate<(all_of FeatureExtZcb),
+ "'Zcb' (Shortened format for basic bit manipulation instructions)">;
+
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">;
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -618,6 +618,16 @@
VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isUImm2Lsb0() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && isShiftedUInt<1, 1>(Imm) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
bool isUImm7Lsb00() const {
if (!isImm())
return false;
@@ -1151,6 +1161,9 @@
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
case Match_InvalidUImm2:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
+ case Match_InvalidUImm2Lsb0:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2,
+ "immediate must be one of");
case Match_InvalidUImm3:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
case Match_InvalidUImm5:
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -113,6 +113,7 @@
{"zbr", RISCVExtensionVersion{0, 93}},
{"zbt", RISCVExtensionVersion{0, 93}},
{"zca", RISCVExtensionVersion{0, 70}},
+ {"zcb", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
};
@@ -778,6 +779,7 @@
static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsZcb[] = {"zca"};
struct ImpliedExtsEntry {
StringLiteral Name;
@@ -793,6 +795,7 @@
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"v"}, {ImpliedExtsV}},
+ {{"zcb"}, {ImpliedExtsZcb}},
{{"zdinx"}, {ImpliedExtsZdinx}},
{{"zfh"}, {ImpliedExtsZfh}},
{{"zfhmin"}, {ImpliedExtsZfhmin}},
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -45,6 +45,8 @@
// CHECK-NOT: __riscv_zk
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
+// CHECK-NOT: __riscv_zca
+// CHECK-NOT: __riscv_zcb
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -462,3 +464,16 @@
// RUN: %clang -target riscv64 -march=rv64izicbop -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOP-EXT %s
// CHECK-ZICBOP-EXT: __riscv_zicbop 1000000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// CHECK-ZCA-EXT: __riscv_zca 70000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// CHECK-ZCB-EXT: __riscv_zca 70000{{$}}
+// CHECK-ZCB-EXT: __riscv_zcb 70000{{$}}
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