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Adding half float to types that can be represented by __attribute__((mode(xx))).
Original implementation authored by George Steed.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126479
Files:
clang/include/clang/Basic/TargetInfo.h
clang/lib/AST/ASTContext.cpp
clang/lib/Basic/TargetInfo.cpp
clang/test/CodeGen/aarch64-attr-mode-complex.c
clang/test/Sema/attr-mode-vector-types.c
clang/test/Sema/attr-mode.c
Index: clang/test/Sema/attr-mode.c
===================================================================
--- clang/test/Sema/attr-mode.c
+++ clang/test/Sema/attr-mode.c
@@ -37,6 +37,11 @@
__attribute__((mode(QI))) int invalid_func(void) { return 1; } // expected-error{{'mode' attribute only applies to variables, enums, typedefs, and non-static data members}}
enum invalid_enum { A1 __attribute__((mode(QI))) }; // expected-error{{'mode' attribute only applies to}}
+typedef _Complex float c16a __attribute((mode(HC)));
+int c16a_test[sizeof(c16a) == 4 ? 1 : -1];
+typedef _Complex double c16b __attribute((mode(HC)));
+int c16b_test[sizeof(c16b) == 4 ? 1 : -1];
+
typedef _Complex double c32 __attribute((mode(SC)));
int c32_test[sizeof(c32) == 8 ? 1 : -1];
typedef _Complex float c64 __attribute((mode(DC)));
Index: clang/test/Sema/attr-mode-vector-types.c
===================================================================
--- clang/test/Sema/attr-mode-vector-types.c
+++ clang/test/Sema/attr-mode-vector-types.c
@@ -22,8 +22,7 @@
// expected-error@-1{{unsupported machine mode 'QC'}}
// expected-error@-2{{type of machine mode does not match type of base type}}
typedef _Complex float __attribute__((mode(HC))) __attribute__((vector_size(256))) vec_t9;
-// expected-error@-1{{unsupported machine mode 'HC'}}
-// expected-error@-2{{invalid vector element type '_Complex float'}}
+// expected-error@-1{{invalid vector element type '_Complex float'}}
typedef int __attribute__((mode(SC))) __attribute__((vector_size(256))) vec_t10;
// expected-error@-1{{type of machine mode does not match type of base type}}
// expected-error@-2{{type of machine mode does not support base vector types}}
Index: clang/test/CodeGen/aarch64-attr-mode-complex.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-attr-mode-complex.c
@@ -0,0 +1,47 @@
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -emit-llvm -Ofast %s -o - | FileCheck %s
+
+typedef _Complex float c16a __attribute((mode(HC)));
+typedef _Complex double c16b __attribute((mode(HC)));
+typedef _Complex float c32a __attribute((mode(SC)));
+typedef _Complex double c32b __attribute((mode(SC)));
+typedef _Complex float c64a __attribute((mode(DC)));
+typedef _Complex double c64b __attribute((mode(DC)));
+
+// CHECK: define{{.*}} { half, half } @c16_test([2 x half] noundef [[C16A:%.*]])
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[C16B:%.*]] = extractvalue [2 x half] [[C16A]], 0
+// CHECK-NEXT: [[C16C:%.*]] = extractvalue [2 x half] [[C16A]], 1
+// CHECK-NEXT: [[C16D:%.*]] = fadd half [[C16B]], [[C16B]]
+// CHECK-NEXT: [[C16E:%.*]] = fadd half [[C16C]], [[C16C]]
+// CHECK-NEXT: [[C16F:%.*]] = insertvalue { half, half } poison, half [[C16D]], 0
+// CHECK-NEXT: [[C16G:%.*]] = insertvalue { half, half } [[C16F]], half [[C16E]], 1
+// CHECK-NEXT: ret { half, half } [[C16G]]
+c16b c16_test(c16a x) {
+ return x + x;
+}
+
+// CHECK: define{{.*}} { float, float } @c32_test([2 x float] noundef [[C32A:%.*]])
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[C32B:%.*]] = extractvalue [2 x float] [[C32A]], 0
+// CHECK-NEXT: [[C32C:%.*]] = extractvalue [2 x float] [[C32A]], 1
+// CHECK-NEXT: [[C32D:%.*]] = fadd float [[C32B]], [[C32B]]
+// CHECK-NEXT: [[C32E:%.*]] = fadd float [[C32C]], [[C32C]]
+// CHECK-NEXT: [[C32F:%.*]] = insertvalue { float, float } poison, float [[C32D]], 0
+// CHECK-NEXT: [[C32G:%.*]] = insertvalue { float, float } [[C32F]], float [[C32E]], 1
+// CHECK-NEXT: ret { float, float } [[C32G]]
+c32b c32_test(c32a x) {
+ return x + x;
+}
+
+// CHECK: define{{.*}} { double, double } @c64_test([2 x double] noundef [[C64A:%.*]])
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[C64B:%.*]] = extractvalue [2 x double] [[C64A]], 0
+// CHECK-NEXT: [[C64C:%.*]] = extractvalue [2 x double] [[C64A]], 1
+// CHECK-NEXT: [[C64D:%.*]] = fadd double [[C64B]], [[C64B]]
+// CHECK-NEXT: [[C64E:%.*]] = fadd double [[C64C]], [[C64C]]
+// CHECK-NEXT: [[C64F:%.*]] = insertvalue { double, double } poison, double [[C64D]], 0
+// CHECK-NEXT: [[C64G:%.*]] = insertvalue { double, double } [[C64F]], double [[C64E]], 1
+// CHECK-NEXT: ret { double, double } [[C64G]]
+c64b c64_test(c64a x) {
+ return x + x;
+}
Index: clang/lib/Basic/TargetInfo.cpp
===================================================================
--- clang/lib/Basic/TargetInfo.cpp
+++ clang/lib/Basic/TargetInfo.cpp
@@ -284,6 +284,8 @@
FloatModeKind TargetInfo::getRealTypeByWidth(unsigned BitWidth,
FloatModeKind ExplicitType) const {
+ if (getHalfWidth() == BitWidth)
+ return FloatModeKind::Half;
if (getFloatWidth() == BitWidth)
return FloatModeKind::Float;
if (getDoubleWidth() == BitWidth)
Index: clang/lib/AST/ASTContext.cpp
===================================================================
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -11742,6 +11742,8 @@
FloatModeKind Ty =
getTargetInfo().getRealTypeByWidth(DestWidth, ExplicitType);
switch (Ty) {
+ case FloatModeKind::Half:
+ return HalfTy;
case FloatModeKind::Float:
return FloatTy;
case FloatModeKind::Double:
Index: clang/include/clang/Basic/TargetInfo.h
===================================================================
--- clang/include/clang/Basic/TargetInfo.h
+++ clang/include/clang/Basic/TargetInfo.h
@@ -56,7 +56,8 @@
Double,
LongDouble,
Float128,
- Ibm128
+ Ibm128,
+ Half
};
/// Fields controlling how types are laid out in memory; these may need to
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