Conanap updated this revision to Diff 340141.
Conanap added a comment.
Updated to remove uncessary `xrsp` and other `xxsldwi` as well
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D100782/new/
https://reviews.llvm.org/D100782
Files:
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
Index: llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
+++ llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
@@ -200,21 +200,19 @@
; CHECK-LABEL: testFloat1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpspn vs0, f1
-; CHECK-NEXT: extsw r3, r6
-; CHECK-NEXT: slwi r3, r3, 2
-; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 3
-; CHECK-NEXT: mffprwz r4, f0
-; CHECK-NEXT: vinswrx v2, r3, r4
+; CHECK-NEXT: extsw r4, r6
+; CHECK-NEXT: slwi r4, r4, 2
+; CHECK-NEXT: mffprwz r3, f0
+; CHECK-NEXT: vinswrx v2, r4, r3
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: testFloat1:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpspn vs0, f1
-; CHECK-BE-NEXT: extsw r3, r6
-; CHECK-BE-NEXT: slwi r3, r3, 2
-; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 3
-; CHECK-BE-NEXT: mffprwz r4, f0
-; CHECK-BE-NEXT: vinswlx v2, r3, r4
+; CHECK-BE-NEXT: extsw r4, r6
+; CHECK-BE-NEXT: slwi r4, r4, 2
+; CHECK-BE-NEXT: mffprwz r3, f0
+; CHECK-BE-NEXT: vinswlx v2, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-P9-LABEL: testFloat1:
@@ -346,7 +344,6 @@
; CHECK-LABEL: testFloatImm1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpspn vs0, f1
-; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-NEXT: xxinsertw v2, vs0, 12
; CHECK-NEXT: xxinsertw v2, vs0, 4
; CHECK-NEXT: blr
@@ -354,7 +351,6 @@
; CHECK-BE-LABEL: testFloatImm1:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpspn vs0, f1
-; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-BE-NEXT: xxinsertw v2, vs0, 0
; CHECK-BE-NEXT: xxinsertw v2, vs0, 8
; CHECK-BE-NEXT: blr
@@ -362,7 +358,6 @@
; CHECK-P9-LABEL: testFloatImm1:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpspn vs0, f1
-; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-P9-NEXT: xxinsertw v2, vs0, 8
; CHECK-P9-NEXT: blr
@@ -393,11 +388,9 @@
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r5)
; CHECK-P9-NEXT: xscvdpspn vs0, f0
-; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-P9-NEXT: lfs f0, 4(r5)
; CHECK-P9-NEXT: xscvdpspn vs0, f0
-; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-P9-NEXT: xxinsertw v2, vs0, 8
; CHECK-P9-NEXT: blr
entry:
@@ -439,11 +432,9 @@
; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: rldic r3, r3, 38, 25
; CHECK-P9-NEXT: xscvdpspn vs0, f0
-; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-P9-NEXT: xxinsertw v2, vs0, 0
; CHECK-P9-NEXT: lfsx f0, r5, r3
; CHECK-P9-NEXT: xscvdpspn vs0, f0
-; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 3
; CHECK-P9-NEXT: xxinsertw v2, vs0, 8
; CHECK-P9-NEXT: blr
entry:
Index: llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
+++ llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
@@ -216,7 +216,6 @@
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfs f0, 0(r3)
; P9LE-NEXT: xscvdpspn vs0, f0
-; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P9LE-NEXT: xxinsertw v2, vs0, 12
; P9LE-NEXT: blr
;
@@ -224,7 +223,6 @@
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfs f0, 0(r3)
; P9BE-NEXT: xscvdpspn vs0, f0
-; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P9BE-NEXT: xxinsertw v2, vs0, 0
; P9BE-NEXT: blr
;
Index: llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
+++ llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
@@ -506,11 +506,9 @@
entry:
; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
; CHECK: xxinsertw 34, 0, 12
; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
; CHECK-BE: xxinsertw 34, 0, 0
%vecins = insertelement <4 x float> %a, float %b, i32 0
ret <4 x float> %vecins
@@ -520,11 +518,9 @@
entry:
; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
; CHECK: xxinsertw 34, 0, 8
; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
; CHECK-BE: xxinsertw 34, 0, 4
%vecins = insertelement <4 x float> %a, float %b, i32 1
ret <4 x float> %vecins
@@ -534,11 +530,9 @@
entry:
; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
; CHECK: xxinsertw 34, 0, 4
; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
; CHECK-BE: xxinsertw 34, 0, 8
%vecins = insertelement <4 x float> %a, float %b, i32 2
ret <4 x float> %vecins
@@ -548,11 +542,9 @@
entry:
; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
; CHECK: xxinsertw 34, 0, 0
; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
; CHECK-BE: xxinsertw 34, 0, 12
%vecins = insertelement <4 x float> %a, float %b, i32 3
ret <4 x float> %vecins
Index: llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
+++ llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
@@ -10,8 +10,8 @@
; CHECK-P7: stfs 1,
; CHECK-P7: lwa 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
}
define i64 @f64toi64(double %a) {
@@ -50,8 +50,8 @@
; CHECK-P7: stfs 1,
; CHECK-P7: lwz 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
}
define i64 @f64toi64u(double %a) {
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1814,8 +1814,7 @@
// Output dag used to bitcast f32 to i32 and f64 to i64
def Bitcast {
- dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI (XSCVDPSPN $A),
- (XSCVDPSPN $A), 3), sub_64)));
+ dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));
dag DblToLong = (i64 (MFVSRD $A));
}
@@ -2210,7 +2209,7 @@
}
def AlignValues {
- dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3));
+ dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B));
dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64);
}
@@ -2794,6 +2793,9 @@
v4i32, FltToUIntLoad.A,
(XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), sub_64), 1),
(SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), sub_64)>;
+def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)),
+ (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))),
+ (v4f32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSP f64:$A), VSRC), 0))>;
def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
(v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;
def : Pat<(v2f64 (PPCldsplat xoaddr:$A)),
@@ -4237,12 +4239,24 @@
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
(v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),
+ (v4f32 (XXINSERTW v4f32:$A,
+ (COPY_TO_REGCLASS (XSCVDPSP f64:$B), VSRC), 12))>;
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),
+ (v4f32 (XXINSERTW v4f32:$A,
+ (COPY_TO_REGCLASS (XSCVDPSP f64:$B), VSRC), 8))>;
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),
+ (v4f32 (XXINSERTW v4f32:$A,
+ (COPY_TO_REGCLASS (XSCVDPSP f64:$B), VSRC), 4))>;
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),
+ (v4f32 (XXINSERTW v4f32:$A,
+ (COPY_TO_REGCLASS (XSCVDPSP f64:$B), VSRC), 0))>;
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
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