FreddyYe updated this revision to Diff 336007.
FreddyYe added a comment.
Updating according to comments. Test refactoring not done.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D100085/new/
https://reviews.llvm.org/D100085
Files:
clang/lib/Basic/Targets/X86.cpp
clang/test/CodeGen/attr-target-mv.c
clang/test/CodeGen/target-builtin-noerror.c
clang/test/Driver/x86-march.c
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/predefined-arch-macros.c
compiler-rt/lib/builtins/cpu_model.c
llvm/include/llvm/Support/X86TargetParser.def
llvm/include/llvm/Support/X86TargetParser.h
llvm/lib/Support/Host.cpp
llvm/lib/Support/X86TargetParser.cpp
llvm/lib/Target/X86/X86.td
llvm/test/CodeGen/X86/cpus-intel.ll
Index: llvm/test/CodeGen/X86/cpus-intel.ll
===================================================================
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -38,6 +38,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=rocketlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -754,7 +754,7 @@
list<SubtargetFeature> ICXFeatures =
!listconcat(ICLFeatures, ICXAdditionalFeatures);
- //Tigerlake
+ // Tigerlake
list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
FeatureMOVDIRI,
FeatureMOVDIR64B,
@@ -763,7 +763,35 @@
list<SubtargetFeature> TGLFeatures =
!listconcat(ICLFeatures, TGLAdditionalFeatures );
- //Sapphirerapids
+ // Rocketlake
+ list<SubtargetFeature> RKLAdditionalFeatures = [FeatureAES,
+ FeatureXSAVEC,
+ FeatureXSAVES,
+ FeatureCLFLUSHOPT,
+ FeatureAVX512,
+ FeatureCDI,
+ FeatureDQI,
+ FeatureBWI,
+ FeatureVLX,
+ FeaturePKU,
+ FeatureVBMI,
+ FeatureIFMA,
+ FeatureSHA,
+ FeatureBITALG,
+ FeatureVAES,
+ FeatureVBMI2,
+ FeatureVNNI,
+ FeatureVPCLMULQDQ,
+ FeatureVPOPCNTDQ,
+ FeatureGFNI,
+ FeatureCLWB,
+ FeatureRDPID,
+ FeatureFSRM];
+ list<SubtargetFeature> RKLTuning = ICLTuning;
+ list<SubtargetFeature> RKLFeatures =
+ !listconcat(BDWFeatures, RKLAdditionalFeatures);
+
+ // Sapphirerapids
list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
FeatureAMXINT8,
FeatureAMXBF16,
@@ -1307,6 +1335,8 @@
ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
def : ProcModel<"icelake-client", SkylakeServerModel,
ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
+def : ProcModel<"rocketlake", SkylakeServerModel,
+ ProcessorFeatures.RKLFeatures, ProcessorFeatures.RKLTuning>;
def : ProcModel<"icelake-server", SkylakeServerModel,
ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
def : ProcModel<"tigerlake", SkylakeServerModel,
Index: llvm/lib/Support/X86TargetParser.cpp
===================================================================
--- llvm/lib/Support/X86TargetParser.cpp
+++ llvm/lib/Support/X86TargetParser.cpp
@@ -194,6 +194,7 @@
FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
+constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
constexpr FeatureBitset FeaturesICLServer =
FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
constexpr FeatureBitset FeaturesTigerlake =
@@ -356,6 +357,8 @@
{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
// Icelake client microarchitecture based processors.
{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
+ // Rocketlake microarchitecture based processors.
+ { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake },
// Icelake server microarchitecture based processors.
{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
// Tigerlake microarchitecture based processors.
Index: llvm/lib/Support/Host.cpp
===================================================================
--- llvm/lib/Support/Host.cpp
+++ llvm/lib/Support/Host.cpp
@@ -708,6 +708,13 @@
*Subtype = X86::INTEL_COREI7_SKYLAKE;
break;
+ // Rocketlake:
+ case 0xa7:
+ CPU = "rocketlake";
+ *Type = X86::INTEL_COREI7;
+ *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
+ break;
+
// Skylake Xeon:
case 0x55:
*Type = X86::INTEL_COREI7;
Index: llvm/include/llvm/Support/X86TargetParser.h
===================================================================
--- llvm/include/llvm/Support/X86TargetParser.h
+++ llvm/include/llvm/Support/X86TargetParser.h
@@ -98,6 +98,7 @@
CK_Cooperlake,
CK_Cannonlake,
CK_IcelakeClient,
+ CK_Rocketlake,
CK_IcelakeServer,
CK_Tigerlake,
CK_SapphireRapids,
Index: llvm/include/llvm/Support/X86TargetParser.def
===================================================================
--- llvm/include/llvm/Support/X86TargetParser.def
+++ llvm/include/llvm/Support/X86TargetParser.def
@@ -88,6 +88,7 @@
X86_CPU_SUBTYPE(INTEL_COREI7_SAPPHIRERAPIDS, "sapphirerapids")
X86_CPU_SUBTYPE(INTEL_COREI7_ALDERLAKE, "alderlake")
X86_CPU_SUBTYPE(AMDFAM19H_ZNVER3, "znver3")
+X86_CPU_SUBTYPE(INTEL_COREI7_ROCKETLAKE, "rocketlake")
#undef X86_CPU_SUBTYPE
Index: compiler-rt/lib/builtins/cpu_model.c
===================================================================
--- compiler-rt/lib/builtins/cpu_model.c
+++ compiler-rt/lib/builtins/cpu_model.c
@@ -99,6 +99,7 @@
INTEL_COREI7_SAPPHIRERAPIDS,
INTEL_COREI7_ALDERLAKE,
AMDFAM19H_ZNVER3,
+ INTEL_COREI7_ROCKETLAKE,
CPU_SUBTYPE_MAX
};
@@ -384,6 +385,12 @@
*Subtype = INTEL_COREI7_SKYLAKE;
break;
+ // Rocketlake:
+ case 0xa7:
+ CPU = "rocketlake";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_COREI7_ROCKETLAKE;
+
// Skylake Xeon:
case 0x55:
*Type = INTEL_COREI7;
Index: clang/test/Preprocessor/predefined-arch-macros.c
===================================================================
--- clang/test/Preprocessor/predefined-arch-macros.c
+++ clang/test/Preprocessor/predefined-arch-macros.c
@@ -1393,6 +1393,121 @@
// CHECK_ICL_M64: #define __x86_64 1
// CHECK_ICL_M64: #define __x86_64__ 1
+// RUN: %clang -march=rocketlake -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_RKL_M32
+// CHECK_RKL_M32: #define __AES__ 1
+// CHECK_RKL_M32: #define __AVX2__ 1
+// CHECK_RKL_M32: #define __AVX512BITALG__ 1
+// CHECK_RKL_M32: #define __AVX512BW__ 1
+// CHECK_RKL_M32: #define __AVX512CD__ 1
+// CHECK_RKL_M32: #define __AVX512DQ__ 1
+// CHECK_RKL_M32: #define __AVX512F__ 1
+// CHECK_RKL_M32: #define __AVX512IFMA__ 1
+// CHECK_RKL_M32: #define __AVX512VBMI2__ 1
+// CHECK_RKL_M32: #define __AVX512VBMI__ 1
+// CHECK_RKL_M32: #define __AVX512VL__ 1
+// CHECK_RKL_M32: #define __AVX512VNNI__ 1
+// CHECK_RKL_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_RKL_M32: #define __AVX__ 1
+// CHECK_RKL_M32: #define __BMI2__ 1
+// CHECK_RKL_M32: #define __BMI__ 1
+// CHECK_RKL_M32: #define __CLFLUSHOPT__ 1
+// CHECK_RKL_M32: #define __CLWB__ 1
+// CHECK_RKL_M32: #define __F16C__ 1
+// CHECK_RKL_M32: #define __FMA__ 1
+// CHECK_RKL_M32: #define __GFNI__ 1
+// CHECK_RKL_M32: #define __INVPCID__ 1
+// CHECK_RKL_M32: #define __LZCNT__ 1
+// CHECK_RKL_M32: #define __MMX__ 1
+// CHECK_RKL_M32: #define __MOVBE__ 1
+// CHECK_RKL_M32: #define __PCLMUL__ 1
+// CHECK_RKL_M32: #define __PKU__ 1
+// CHECK_RKL_M32: #define __POPCNT__ 1
+// CHECK_RKL_M32: #define __PRFCHW__ 1
+// CHECK_RKL_M32: #define __RDPID__ 1
+// CHECK_RKL_M32: #define __RDRND__ 1
+// CHECK_RKL_M32: #define __RDSEED__ 1
+// CHECK_RKL_M32-NOT: #define __SGX__ 1
+// CHECK_RKL_M32: #define __SHA__ 1
+// CHECK_RKL_M32: #define __SSE2__ 1
+// CHECK_RKL_M32: #define __SSE3__ 1
+// CHECK_RKL_M32: #define __SSE4_1__ 1
+// CHECK_RKL_M32: #define __SSE4_2__ 1
+// CHECK_RKL_M32: #define __SSE__ 1
+// CHECK_RKL_M32: #define __SSSE3__ 1
+// CHECK_RKL_M32: #define __VAES__ 1
+// CHECK_RKL_M32: #define __VPCLMULQDQ__ 1
+// CHECK_RKL_M32-NOT: #define __WBNOINVD__ 1
+// CHECK_RKL_M32: #define __XSAVEC__ 1
+// CHECK_RKL_M32: #define __XSAVEOPT__ 1
+// CHECK_RKL_M32: #define __XSAVES__ 1
+// CHECK_RKL_M32: #define __XSAVE__ 1
+// CHECK_RKL_M32: #define __corei7 1
+// CHECK_RKL_M32: #define __corei7__ 1
+// CHECK_RKL_M32: #define __i386 1
+// CHECK_RKL_M32: #define __i386__ 1
+// CHECK_RKL_M32: #define __tune_corei7__ 1
+// CHECK_RKL_M32: #define i386 1
+
+// RUN: %clang -march=rocketlake -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_RKL_M64
+// CHECK_RKL_M64: #define __AES__ 1
+// CHECK_RKL_M64: #define __AVX2__ 1
+// CHECK_RKL_M64: #define __AVX512BITALG__ 1
+// CHECK_RKL_M64: #define __AVX512BW__ 1
+// CHECK_RKL_M64: #define __AVX512CD__ 1
+// CHECK_RKL_M64: #define __AVX512DQ__ 1
+// CHECK_RKL_M64: #define __AVX512F__ 1
+// CHECK_RKL_M64: #define __AVX512IFMA__ 1
+// CHECK_RKL_M64: #define __AVX512VBMI2__ 1
+// CHECK_RKL_M64: #define __AVX512VBMI__ 1
+// CHECK_RKL_M64: #define __AVX512VL__ 1
+// CHECK_RKL_M64: #define __AVX512VNNI__ 1
+// CHECK_RKL_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_RKL_M64: #define __AVX__ 1
+// CHECK_RKL_M64: #define __BMI2__ 1
+// CHECK_RKL_M64: #define __BMI__ 1
+// CHECK_RKL_M64: #define __CLFLUSHOPT__ 1
+// CHECK_RKL_M64: #define __CLWB__ 1
+// CHECK_RKL_M64: #define __F16C__ 1
+// CHECK_RKL_M64: #define __FMA__ 1
+// CHECK_RKL_M64: #define __GFNI__ 1
+// CHECK_RKL_M64: #define __INVPCID__ 1
+// CHECK_RKL_M64: #define __LZCNT__ 1
+// CHECK_RKL_M64: #define __MMX__ 1
+// CHECK_RKL_M64: #define __MOVBE__ 1
+// CHECK_RKL_M64: #define __PCLMUL__ 1
+// CHECK_RKL_M64: #define __PKU__ 1
+// CHECK_RKL_M64: #define __POPCNT__ 1
+// CHECK_RKL_M64: #define __PRFCHW__ 1
+// CHECK_RKL_M64: #define __RDPID__ 1
+// CHECK_RKL_M64: #define __RDRND__ 1
+// CHECK_RKL_M64: #define __RDSEED__ 1
+// CHECK_RKL_M64-NOT: #define __SGX__ 1
+// CHECK_RKL_M64: #define __SHA__ 1
+// CHECK_RKL_M64: #define __SSE2__ 1
+// CHECK_RKL_M64: #define __SSE3__ 1
+// CHECK_RKL_M64: #define __SSE4_1__ 1
+// CHECK_RKL_M64: #define __SSE4_2__ 1
+// CHECK_RKL_M64: #define __SSE__ 1
+// CHECK_RKL_M64: #define __SSSE3__ 1
+// CHECK_RKL_M64: #define __VAES__ 1
+// CHECK_RKL_M64: #define __VPCLMULQDQ__ 1
+// CHECK_RKL_M64-NOT: #define __WBNOINVD__ 1
+// CHECK_RKL_M64: #define __XSAVEC__ 1
+// CHECK_RKL_M64: #define __XSAVEOPT__ 1
+// CHECK_RKL_M64: #define __XSAVES__ 1
+// CHECK_RKL_M64: #define __XSAVE__ 1
+// CHECK_RKL_M64: #define __amd64 1
+// CHECK_RKL_M64: #define __amd64__ 1
+// CHECK_RKL_M64: #define __corei7 1
+// CHECK_RKL_M64: #define __corei7__ 1
+// CHECK_RKL_M64: #define __tune_corei7__ 1
+// CHECK_RKL_M64: #define __x86_64 1
+// CHECK_RKL_M64: #define __x86_64__ 1
+
// RUN: %clang -march=icelake-server -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICX_M32
Index: clang/test/Misc/target-invalid-cpu-note.c
===================================================================
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -21,7 +21,7 @@
// X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
// X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
@@ -33,7 +33,7 @@
// X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
// X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
// X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake,
-// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
+// X86_64-SAME: icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
// X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1,
// X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
// X86_64-SAME: x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}}
@@ -46,7 +46,7 @@
// TUNE_X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// TUNE_X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// TUNE_X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
// TUNE_X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// TUNE_X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// TUNE_X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
@@ -60,7 +60,7 @@
// TUNE_X86_64-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
// TUNE_X86_64-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
// TUNE_X86_64-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3,
// TUNE_X86_64-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
// TUNE_X86_64-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
// TUNE_X86_64-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3,
Index: clang/test/Driver/x86-march.c
===================================================================
--- clang/test/Driver/x86-march.c
+++ clang/test/Driver/x86-march.c
@@ -72,6 +72,10 @@
// RUN: | FileCheck %s -check-prefix=icelake-client
// icelake-client: "-target-cpu" "icelake-client"
//
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=rocketlake 2>&1 \
+// RUN: | FileCheck %s -check-prefix=rocketlake
+// rocketlake: "-target-cpu" "rocketlake"
+//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-server 2>&1 \
// RUN: | FileCheck %s -check-prefix=icelake-server
// icelake-server: "-target-cpu" "icelake-server"
Index: clang/test/CodeGen/target-builtin-noerror.c
===================================================================
--- clang/test/CodeGen/target-builtin-noerror.c
+++ clang/test/CodeGen/target-builtin-noerror.c
@@ -116,6 +116,7 @@
(void)__builtin_cpu_is("knl");
(void)__builtin_cpu_is("knm");
(void)__builtin_cpu_is("nehalem");
+ (void)__builtin_cpu_is("rocketlake");
(void)__builtin_cpu_is("sandybridge");
(void)__builtin_cpu_is("shanghai");
(void)__builtin_cpu_is("silvermont");
Index: clang/test/CodeGen/attr-target-mv.c
===================================================================
--- clang/test/CodeGen/attr-target-mv.c
+++ clang/test/CodeGen/attr-target-mv.c
@@ -13,6 +13,7 @@
int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;}
int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
int __attribute__((target("arch=alderlake"))) foo(void) {return 11;}
+int __attribute__((target("arch=rocketlake"))) foo(void) {return 12;}
int __attribute__((target("default"))) foo(void) { return 2; }
int bar() {
@@ -97,6 +98,8 @@
// LINUX: ret i32 10
// LINUX: define{{.*}} i32 @foo.arch_alderlake()
// LINUX: ret i32 11
+// LINUX: define{{.*}} i32 @foo.arch_rocketlake()
+// LINUX: ret i32 12
// LINUX: define{{.*}} i32 @foo()
// LINUX: ret i32 2
// LINUX: define{{.*}} i32 @bar()
Index: clang/lib/Basic/Targets/X86.cpp
===================================================================
--- clang/lib/Basic/Targets/X86.cpp
+++ clang/lib/Basic/Targets/X86.cpp
@@ -467,6 +467,7 @@
case CK_Cooperlake:
case CK_Cannonlake:
case CK_IcelakeClient:
+ case CK_Rocketlake:
case CK_IcelakeServer:
case CK_Tigerlake:
case CK_SapphireRapids:
@@ -1314,6 +1315,7 @@
case CK_Tigerlake:
case CK_SapphireRapids:
case CK_IcelakeClient:
+ case CK_Rocketlake:
case CK_IcelakeServer:
case CK_Alderlake:
case CK_KNL:
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