aaron.ballman added a comment.
In D73967#2653042 <https://reviews.llvm.org/D73967#2653042>, @keryell wrote:
> An FPGA programmer is hitting this issue from your unit test:
>
> c++
> signed _ExtInt(1) m; // expected-error{{signed _ExtInt must have a bit
> size of at least 2}}
>
> Why do you not allow a type able to represent `{-1, 0}`?
At the time this feature was first being designed for WG14, I believe ones
complement and sign magnitude integer representations were still allowed, so a
signed 1-bit _ExtInt made no sense. That's no longer the case and so WG14 may
be more interested in hearing about this if you have a compelling use case.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D73967
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