erichkeane added a comment.
In D73967#2653042 <https://reviews.llvm.org/D73967#2653042>, @keryell wrote:
> An FPGA programmer is hitting this issue from your unit test:
>
> c++
> signed _ExtInt(1) m; // expected-error{{signed _ExtInt must have a bit
> size of at least 2}}
>
> Why do you not allow a type able to represent `{-1, 0}`?
Our FPGA team didn't see any value in it, so we didn't propose it to WG14, so
we didn't implement it here. I'm sure a follow-up paper to WG14 would be
considered, and if it shows promise/positive reception, we'd welcome a patch
here.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D73967/new/
https://reviews.llvm.org/D73967
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