fpallares added a comment. Hi Kai, I've added an inline comment regarding constraint validation:
================ Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2283 + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" ---------------- In this function we are validating the overlap constraints by checking whether `DestReg` matches a vector operand. However, for widenings and narrowings those checks should be extended to validate that the operand doesn't belong to the same register group. For instance: `vwadd.vv v4, v4, v7`: The current code would give an error for this instruction. `vwadd.vv v4, v5, v7`: There would be no error for this, even though `v5` will always overlap with any widened group of `v4`. `vwadd.vv v4, v6, v7`: This should not emit any diagnostic because we can't really tell at this point if there will be an overlap. Perhaps we are already checking this somewhere else and I missed it? (Note that this will probably change with fractional LMUL in 0.9) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
