Hi Dan,
Quite right! Xilinx(AMD) do the VIRTEXTM-7 XC7V2000T with a maximum of 576 differential I/O pairs, the XC7VX1140T with a maximum of 528 Differential I/O pairs, and the VIRTEXTM ULTRASCALE XCVU440 with a maximum of 648 differential HP I/O pairs. Altera (Intel) do the Stratix 10 GX with a maximum of 1152 LVDS pairs running at 1.4 Gbps. Thanks, Neil From: [email protected] <[email protected]> On Behalf Of Dan Werthimer Sent: 11 November 2023 21:30 To: [email protected] Subject: Re: [casper] state of the art single bit correlators hi neil, for a single frequency channel correlator (continuum correlator), an XF architecture (lag correlator) is the way to go, the number of antennas in your correlator will likely be limited by the number of signals you can get into the FPGA. (the correlator will be I/O bound, not compute bound, assuming you have a large FPGA). i haven't looked at the number of LVDS inputs available on a large FPGA recently, but i think for a ~1800 pin package, there might be up to ~~512 LVDS pairs (1024 pins). if so, you can have 512 digitizers, which is 256 complex digitizers, which is 128 antennas dual pol, or 256 antenna single pol. as david hawkins suggested, could also use the high speed serdes on the FPGA. the new pricy FPGAs have serdes that can work at >100 Gbps. and the larger pricy FPGAs have 32 of these serdes, which means you can send 3.2 Tbits/sec into those FGPAs. that data rate is 3200 real 1Gsps bit streams, or 1600 complex streams at 1Gcomplexsamples/sec, or 800 antennas dual pol. but it would take a lot of electronics to convert 100 1Gbit/sec signals into a 100Gbit/sec signal - the easiest way to convert 100 signals into a single 100Gsps signal would be to use an FPGA, and that would defeat your goal of using a single FPGA for your correlator. best wishes, dan On Sat, Nov 11, 2023 at 12:43 PM salmon.na <http://salmon.na> via [email protected] <mailto:[email protected]> <[email protected] <mailto:[email protected]> > wrote: Thanks Dan, Yes, one antenna for one receiver, and there is only one frequency channel, and a single polarisation, so quite a simple configuration. A good idea to use differential inputs as single bit ADCs. So the FX correlator looks the better architecture. So are you saying the FPGA FX correlator would manage making the cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, Xilinx or Altera ? Cheers, Neil From: [email protected] <mailto:[email protected]> <[email protected] <mailto:[email protected]> > On Behalf Of Dan Werthimer Sent: 11 November 2023 20:23 To: [email protected] <mailto:[email protected]> Subject: Re: [casper] state of the art single bit correlators hi neil, by number of receiver channels, i presume you mean number of antennas? are these single or dual polarization? how many spectral channels do you need in your correlator ? for a large number of spectral channels, you'll likely want to use an FX architecture correlator (not XF). in an FX correlator the number of ADC bits doesn't change the FPGA utilization for the DSP very much. one fun thing you can do with a 1 bit correlator, is use the LVDS differential inputs on the FPGA as 1 Gsps digitizers. on a large FPGA with a lot of pins you can get about 512 ADC's (256 antennas, dual pol) built into the FPGA, so the FPGA can be your digitizer and your correlator... if you only need a small number of spectral channels, you could build an XF correlator with ~512 inputs... (~256 antennas, dual pol, or ~512 antennas single pol) in a large FPGA. with an XF architecture, the FPGA utilization is J x number_of_spectral_channels. for FX, the utilization goes as K x log_base_2(spectral_channels). but constant K >> constant J, so sometimes (rarely) it is better to use XF, depending on the number of spectral channels. best wishes, dan On Sat, Nov 11, 2023 at 11:47 AM salmon.na <http://salmon.na> via [email protected] <mailto:[email protected]> <[email protected] <mailto:[email protected]> > wrote: For a paper on non-radioastronomy aperture synthesis technology I need to know how many receiver channels can run into an almost top of the range FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So each receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if there are scaling laws for this and I only need to have a ball park figure, ie a precision of say a factor of three or thereabouts. Any associate papers related to that which might have clues to the capabilities would be helpful. Many thanks, Neil Salmon -- You received this message because you are subscribed to the Google Groups "[email protected] <mailto:[email protected]> " group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected] <mailto:[email protected]> . To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk?utm_medium=email&utm_source=footer> . -- You received this message because you are subscribed to the Google Groups "[email protected] <mailto:[email protected]> " group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected] <mailto:[email protected]> . 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